A scheme to reduce active leakage power by detecting state transitions

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Usami, Kimiyoshi ^a   Yoshioka, Hiroshi ^b  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

Active leakage; Burn in testing; Low power design; Scaling

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; MICROELECTRONICS; TRANSISTORS; VLSI CIRCUITS;

ACTIVE LEAKAGE; BURN-IN TESTING; FINITE-STATE-MACHINES (FSM); LOW-POWER DESIGN;

LEAKAGE CURRENTS;

EID: 11144230990     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. N. Kim, et al, "Leakage Current: Moore's Law Meets Static Power", IEEE Computer, vol.36, no. 12, pp.68-75, Dec.2003.
2. S.Mutoh et al, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE JSSC, vol.30, no.8, pp.847- 854, Aug.1995.
3. R. Vollertsen, "Burn-In", IEEE International Integrated Reliability Workshop Final Report, pp. 167-173, 1999.
4. C. Kim and K. Roy, "Dynamic Vth Scaling Scheme for Active Leakage Power Reduction", DATE'02, 2002.
5. J. Tschanz, et al, "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors", IEEE JSSC, vol.38, no. 11, pp.1838-1845, Nov. 2003.
6. [Online] Available: http://www.cbl.ncsu.edu/