Automatic gate biasing of an SCCMOS power switch achieving maximum leakage reduction and lowering leakage current variability

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 7, 2008, Pages 1688-1698

  Valentian, Alexandra ^a   Beigné, Edith ^a  

^a CEA GRENOBLE   (France)

Author keywords

Leakage currents; Power switch; SCCMOS polarization; Time ranging circuits variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); OPTICAL DESIGN; PROCESS DESIGN; PROCESS ENGINEERING; TRANSISTORS;

(E ,3E) PROCESS; 65NM TECHNOLOGY; AMBIENT TEMPERATURES; APPLIED (CO); BREAKDOWN (BD); CURRENT VARIABILITY; CUT-OFF; ENVIRONMENT CONDITIONS; IN ORDER; LEAKAGE CURRENT REDUCTION; LEAKAGE REDUCTION; LOW SUPPLY VOLTAGES; LOW THRESHOLD VOLTAGE; OPERATING CONDITIONS; ORDERS-OF-MAGNITUDE; POWER DISSIPATIONS; POWER SWITCHING; VOLTAGE STRESSING;

LEAKAGE CURRENTS;

EID: 46749132264     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.922710     Document Type: Conference Paper

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