Interconnect and circuit modeling techniques for full-chip power supply noise analysis

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 21, Issue 3, 1998, Pages 209-215

  Chen, Howard H ^a   Neely, J Scott ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuit simulation; Decoupling capacitor; Delta I noise; Interconnect modeling; Power supply noise; Signal integrity; Switching noise

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

FULL CHIP POWER SUPPLY; INDUCTIVE DELTA CURRENT NOISE; RESISTIVE CURRENT RESISTANCE DROP;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0032136312     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.704931     Document Type: Article

References (15)

1. K. Shepard and V. Narayanan, "Noise in deep submicron digital design," in Dig. Tech. Papers, IEEE Int. Conf. Computer-Aided Design, Nov. 1996, pp. 524-531.
2. R. Sechler and G. Grohoski, "Design at the system level with VLSI CMOS," IBM J. Res. Develop., vol. 39, no. 1, pp. 5-22, Jan. 1995.
3. A. Deutsch et al., "Modeling and characterization of long on-chip interconnections for high-performance microprocessors," IBM J. Res. Develop., vol. 39, no. 5, pp. 547-567, 1995.
4. _, "Design guidelines for short, medium, and long on-chip interconnections," in Proc. IEEE 5th Topic Meeting Elect. Performance Electron. Packag., Oct. 1996, pp. 30-32.
5. _, "The importance of inductance and inductive coupling for on-chip wiring," in Proc. IEEE 6th Topic Meeting Elect. Performance Electron. Packag., Oct. 1997, pp. 53-56.
6. J. Libous and D. O'Connor, "Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 20, pp. 266-271, Aug. 1997.
7. L. Miller, "Controlled collapse reflow chip joining," IBM J. Res. Develop., vol. 13, no. 3, pp. 239-250, 1969.
8. B. McCredie and W. Becker, "Modeling, measurement, and simulation of simultaneous switching noise," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 19, pp. 461-472, Aug. 1996.
9. G. Katopis et al., "Delta-I modeling approximation for single chip modules," in Proc. IEEE 5th Topic Meeting Elect. Performance Electron. Packag., Oct. 1996, pp. 111-113.
10. M. Cases et al., "Delta-I noise avoidance methodology for high performance chip designs," in Proc. IEEE 6th Topic Meeting Electric. Performance Electron. Packag., Oct. 1997, pp. 27-30.
11. A. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM J. Res. Develop., vol. 16, no. 5, pp. 470-481, Sept. 1972.
12. P. Brennan et al., "Three-dimensional inductance computations with partial element equivalent circuits," IBM J. Res. Develop., vol. 23, no. 6, pp. 661-668, Nov. 1979.
13. J. Janak et al., "C3DSTAR: A 3D wiring capacitance calculator," in Dig. Tech. Papers, Int. Conf. Computer-Aided Design, 1989, pp. 530-533.
14. B. Rubin, "An electromagnetic approach for modeling high-performance computer packages," IBM J. Res. Develop., vol. 34, no. 4, pp. 585-600, July 1990.
15. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.