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Volumn , Issue , 2002, Pages 202-206

Automated selective multi-threshold design for ultra-low standby applications

Author keywords

Automated design; Multi threshold; Standby leakage current

Indexed keywords

CELLULAR TELEPHONE SYSTEMS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; DIGITAL SIGNAL PROCESSING; ELECTRIC BATTERIES; GATES (TRANSISTOR); LEAKAGE CURRENTS; MICROPROCESSOR CHIPS;

EID: 0036957192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146737     Document Type: Conference Paper
Times cited : (65)

References (6)
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    • (1997) DAC-97 , pp. 409-414
    • Kao, J.1    Chandrakasan, A.2    Antoniadis, D.3
  • 2
    • 0033359156 scopus 로고    scopus 로고
    • Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's
    • A. Keshavarzi, et al., "Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction in CMOS IC's", ISLPED'99, pp.252-253, 1999.
    • (1999) ISLPED'99 , pp. 252-253
    • Keshavarzi, A.1
  • 3
    • 0030285492 scopus 로고    scopus 로고
    • 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
    • Nov.
    • 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme", IEEE J. Solid-State Circuits, vol.31, pp.1770-1779, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1770-1779
    • Kuroda, T.1
  • 4
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • Aug.
    • S.Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE JSSC, vol.30, no.8, pp.847-854, Aug. 1995.
    • (1995) IEEE JSSC , vol.30 , Issue.8 , pp. 847-854
    • Mutoh, S.1    Douseki, T.2    Matsuya, Y.3    Aoki, T.4    Shigematsu, S.5    Yamada, J.6
  • 5
    • 0003685822 scopus 로고    scopus 로고
    • Low-power CMOS VLSI circuit design
    • John Wiley & Sons, Inc.
    • K. Roy and S. Prasad, "Low-Power CMOS VLSI Circuit Design", pp.214-222, John Wiley & Sons, Inc., 2000.
    • (2000) , pp. 214-222
    • Roy, K.1    Prasad, S.2
  • 6
    • 0031635596 scopus 로고    scopus 로고
    • Design and optimization of low voltage high performance dual threshold CMOS circuits
    • L. Wei, Z. Chen, M. Johnson, K. Roy, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits", DAC-98, pp.489-494, 1998.
    • (1998) DAC-98 , pp. 489-494
    • Wei, L.1    Chen, Z.2    Johnson, M.3    Roy, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.