Supply switching with ground collapse: Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 7, 2007, Pages 758-766

  Shin, Youngsoo ^a,b   Heo, Sewan ^c   Kim, Hyung Ock ^a,b   Choi, Jung Yun ^a,d  

^a Korea Advanced Institute of Science and Technology ^*

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^d SAMSUNG Electronics   (South Korea)

Author keywords

Leakage; Low power; Power gating; Semicustom; Standard cell

Indexed keywords

DATA REDUCTION; LEAKAGE CURRENTS; NANOELECTRONICS; NETWORK ARCHITECTURE; STANDBY POWER SYSTEMS;

INTERFACE CIRCUITS; STANDARD-CELL ELEMENTS; SUPPLY SWITCHING;

CMOS INTEGRATED CIRCUITS;

EID: 34347245249     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.899228     Document Type: Article

References (21)

1. B. H. Calhoun and A. P. Chandrakasan, "Standby power reduction using dynamic voltage scaling and canary flip-flop structures," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1504-1511, Sep. 2004.
2. t) scheme," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1770-1779, Nov. 1996.
3. L. T. Clark, M. Morrow, and W. Brown, "Reverse-body bias and supply collapse for low effective standby power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 947-956, Sep. 2004.
4. t CMOS circuits," in Proc. Symp. VLSI Circuits, 1998, pp. 44-45.
5. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "A 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State. Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
6. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration," in Proc. Custom Integr. Circuits Conf., 2000, pp. 409-412.
7. H. Kawaguchi, K. Nose, and T. Sakurai, "A super cut-off CMOS (SC-CMOS) scheme for 0.5-V supply voltage with picoampere current," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1498-1501-, Oct. 2000.
8. K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, "Automated selective multi-threshold design for ultra-low standby applications," in Proc. Int. Symp. Low-Power Electron. Design, 2002, pp. 202-206.
9. K.-S. Min, H. Kawaguchi, and T. Sakurai, "Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era," in Proc. IEEE Int. Solid-State Circuits Conf., 2003, pp. 400-401.
10. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861-869, Jun. 1997.
11. S.V. Kosonocky, M. Immediato, P. Cottrell, and T. Hook, "Enhanced multi-threshold (MTCMOS) circuits using variable well bias," in Proc. Int. Symp. Low-Power Electron. Design, 2001, pp. 165-169.
12. H.-S. Won, K.-S. Kim, K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong, "An MTCMOS design methodology and its application to mobile computing," in Proc. Int. Symp. Low-Power Electron. Design, 2003, pp. 110-115.
13. P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Boue-tel, J. Blasquez, H. Clasen, G. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, and U. Ko, "90 nm low leakage SoC design techniques for wireless applications," in Proc. IEEE Int. Solid-State Circuits Conf., 2006, pp. 138-139.
14. N. Sirisantana and K. Roy, "Low-power design using multiple channel lengths and oxide thicknesses," IEEE Design Test Comput., vol. 21, no. 1, pp. 56-63, Jan. 2004.
15. S. G. Marendra and A. Chandrakasan, Eds., Leakage in Nanometer CMOS Technologies. New York: Springer, 2005.
16. J. Kao and A. Chandrakasan, "MTCMOS sequential circuits," in Proc. Eur. Solid-State Circuits Conf., 2001, pp. 317-320.
17. S. Mutoh, S. Shigematsu, Y. Gotoh, and S. Konaka, "Design method of MTCMOS power switch for low-voltage high-speed LSIs," in Proc. Asia South Pacific Design Autom. Conf., 1999, pp. 113-116.
18. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design,"in Proc. Custom Integr. Circuits Conf., 2000, pp. 201-204.
19. H.-O. Kim, Y. Shin, H. Kim, and I. Eo, "Physical design methodology of power gating circuits for standard-cell-based design," in Proc. Design Autom. Conf., 2006, pp. 109-112.
20. R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, "High-performance and low-power challenges for sub-70 nm microprocessor circuits," in Proc. Custom Tntegr. Circuits Conf., 2002, pp. 125-128.
21. ARM, Cambridge, U.K., "Embedded tracemacrocell," [Online]. Available: http://www.arm.com/products/solutions/ETM.html