A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 689-692

  Rao, Rahul M ^a   Liu, Frank ^b   Burns, Jeffrey L ^b   Brown, Richard B ^a  

^a University of Michigan   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; HEURISTIC METHODS; LEAKAGE CURRENTS; VECTORS;

LEAKAGE POWER; LEAKAGE VECTOR; POWER CONSUMPTION;

COMBINATORIAL CIRCUITS;

EID: 0346778724     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159754     Document Type: Conference Paper

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