Low power integrated scan-retention mechanism

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 98-102

  Zyuban, Victor ^a   Kosonocky, Stephen V ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Balloon latch; Data retention; Latch; Leakage; Low power; MTCMOS; Scan; Subthreshold

Indexed keywords

FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC GATES; MICROPROCESSOR CHIPS; SEQUENTIAL CIRCUITS;

DATA RETENTION; LATCH; LOW POWER; MULTI-THRESHOLD CMOS; SCAN; SUBTHRESHOLD;

CMOS INTEGRATED CIRCUITS;

EID: 0036958067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146719     Document Type: Conference Paper

References (13)

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