A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 6, 1997, Pages 861-869

  Shigematsu, Satoshi ^a,b,c,d   Mutoh, Shin'ichiro ^a,b,e,f   Matsuya, Yasuyuki ^a,b,g,h   Tanabe, Yasuyuki ^b,i,j,k   Yamada, Junzo ^a,b,f,h,j  

^a IEEE   (Japan)

^b NTT CORPORATION   (Japan)

^c TOKYO DENKI UNIVERSITY   (Japan)

^d IPSJ   (Japan)

^e CHIBA UNIVERSITY   (Japan)

^f Institute of Electronics   (Japan)

^g IWATE UNIVERSITY   (Japan)

^h University of Tokyo   (Japan)

ⁱ WASEDA UNIVERSITY   (Japan)

^j Musashino Electrical Communication Lab   (Japan)

^k JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

more..

Author keywords

Circuit design; Circuit optimization; CMOS digital integrated circuits; Flip flops; Low power circuit; Low voltage CMOS

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DIGITAL INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; LSI CIRCUITS; MOSFET DEVICES; POWER SUPPLY CIRCUITS;

CIRCUIT OPTIMIZATION; CMOS DIGITAL INTEGRATED CIRCUITS; MULTITHRESHOLD VOLTAGE CMOS CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0031162017     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.585288     Document Type: Article

References (8)

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7. T. Sakata, K. Itoh, and M. Horiguchi, "Subthreshold-current reduction circuits for multi-gigabit DRAM's," IEEE J. Solid-State Circuits, vol. 29, pp. 761-769, July 1994.
8. S. Shigematsu, S. Mutoh, Y. Matsuya, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down applications," in IEEE 1995 Symp. Circuits Dig. Tech. Papers, June 1995, pp. 125-126.