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Volumn 2006, Issue , 2006, Pages 570-575

Delay modeling and static timing analysis for MTCMOS circuits

Author keywords

Delay; Interpolation; Leakage power; MTCMOS; Selective MT; Static timing analysis

Indexed keywords

INTERPOLATION; MATHEMATICAL MODELS; POWER SUPPLY CIRCUITS;

EID: 33748588117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118435     Document Type: Conference Paper
Times cited : (6)

References (7)
  • 1
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," J. of Solid State Circuits, vol.30(8), pp.847-854, 1995.
    • (1995) J. of Solid State Circuits , vol.30 , Issue.8 , pp. 847-854
    • Mutoh, S.1    Douseki, T.2    Matsuya, Y.3    Aoki, T.4    Shigematsu, S.5    Yamada, J.6
  • 2
    • 0036957192 scopus 로고    scopus 로고
    • Automated selective multi-threshold design for ultra-low standby applications
    • August
    • K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, "Automated Selective Multi-Threshold Design for Ultra-Low Standby Applications," in Proc. ISLPED, pp.202-206, August 2002.
    • (2002) Proc. ISLPED , pp. 202-206
    • Usami, K.1    Kawabe, N.2    Koizumi, M.3    Seta, K.4    Furusawa, T.5
  • 3
    • 33646919151 scopus 로고    scopus 로고
    • Area-efficient selective multi-threshold CMOS design methodology for standby leakage power reduction
    • T. Kitahara, N. Kawabe, F. Minami, K. Seta, and T. Furusawa, "Area-efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction," in Proc. DATE, pp.646-647, 2005.
    • (2005) Proc. DATE , pp. 646-647
    • Kitahara, T.1    Kawabe, N.2    Minami, F.3    Seta, K.4    Furusawa, T.5
  • 4
    • 0030697754 scopus 로고    scopus 로고
    • Transistor sizing issues and tools for multi-threshold CMOS technology
    • J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor Sizing Issues and Tools for Multi-Threshold CMOS Technology," in Proc. DAC, pp.409-414, 1997.
    • (1997) Proc. DAC , pp. 409-414
    • Kao, J.1    Chandrakasan, A.2    Antoniadis, D.3
  • 5
    • 33748605727 scopus 로고    scopus 로고
    • Analysis on MTCMOS circuit based on lamped RC model for virtual ground line
    • K. Usami, N. Ohkubo, and M. Shirakawa, "Analysis on MTCMOS Circuit based on Lamped RC Model for Virtual Ground Line," in Proc. ISOCC, pp.116-119, 2005.
    • (2005) Proc. ISOCC , pp. 116-119
    • Usami, K.1    Ohkubo, N.2    Shirakawa, M.3
  • 7
    • 33748606516 scopus 로고    scopus 로고
    • The processor IP for research with software development environment
    • in Japanese
    • Y. Mitani, H. Uchida, T. Hironaka, J. MattauschHans, and T. Koide, "The Processor IP for Research with Software Development Environment," Technical Report of IEICE, VLD2001-109, pp. 121-126, 2001. (in Japanese)
    • (2001) Technical Report of IEICE , vol.VLD2001-109 , pp. 121-126
    • Mitani, Y.1    Uchida, H.2    Hironaka, T.3    MattauschHans, J.4    Koide, T.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.