Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 252-254

  Keshavarzi, Ali ^a   Narendra, Siva ^a   Borkar, Shekhar ^a   Hawkins, Charles ^a   Roy, Kaushik ^a   De, Vivek ^a  

^a UNIVERSITY OF NEW MEXICO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSERVATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS;

REVERSE BODY BIAS;

CMOS INTEGRATED CIRCUITS;

EID: 0033359156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313937     Document Type: Article

References (7)