Charge recycling in power-gated CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 10, 2008, Pages 1798-1811

  Pakbaznia, Ehsan ^a,b   Fallah, Farzan ^a,c   Pedram, Massoud ^a,b  

^a IEEE

^b University of Southern California ^*  (United States)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Charge recycling; Leakage; Low power; Multi threshold CMOS (MTCMOS); Power gating; Very large scale integration (VLSI)

Indexed keywords

LEAKAGE CURRENTS; NETWORKS (CIRCUITS); RECYCLING; VLSI CIRCUITS;

CHALLENGING TASK; CHARGE RECYCLING; CMOS CIRCUITS; DYNAMIC ENERGY; GROUND BOUNCE; LEAKAGE; LOW POWER; MODE TRANSITIONS; MULTI-THRESHOLD CMOS (MTCMOS); NEGATIVE VOLTAGES; POWER GATING; POWER GATING STRUCTURE; SETTLING TIME; SLEEP MODES; VERY LARGE SCALE INTEGRATION (VLSI); VERY LARGE-SCALE INTEGRATION; VIRTUAL POWER;

ENERGY CONSERVATION;

EID: 52649104913     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2003297     Document Type: Article

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