Optimizing drain current, inversion level, and channel length in analog CMOS design

Analog Integrated Circuits and Signal Processing

Volumn 47, Issue 2, 2006, Pages 137-163

  Binkley, D M ^a   Blalock, B J ^b   Rochelle, J M ^c  

^a University of North Carolina at Charlotte   (United States)

^b University of Tennessee Knoxville   (United States)

^c Siemens Medical Solutions ^*  (United States)

Author keywords

Analog MOS; And strong inversion; CMOS design; Dc voltage and current mismatch; Design methodology; Early voltage; Intrinsic bandwidth; Intrinsic voltage gain; Moderate; MOS sizing; Optimization; Thermal and flicker noise; Tiransconductance efficiency; Weak

Indexed keywords

ANALOG MOS; DESIGN METHODOLOGY; EARLY VOLTAGE; INTRINSIC BANDWIDTH; INTRINSIC VOLTAGE GAIN; STRONG INVERSION; THERMAL AND FLICKER NOISE; TIRANSCONDUCTANCE EFFICIENCY; WEAK INVERSION;

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CURRENT VOLTAGE CHARACTERISTICS; DC TRANSFORMERS; ELECTRIC POTENTIAL; FLICKERING; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; OPTIMIZATION; THERMAL NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 33646553021     PISSN: 09251030     EISSN: 15731979     Source Type: Journal    
DOI: 10.1007/s10470-006-2949-y     Document Type: Article

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