Impact of process scaling on 1/f noise in advanced CMOS technologies

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 463-466

  Knitel, M J ^a   Woerlee, P H ^a   Scholten, A J ^a   Zegers Van Duijnhoven, A T A ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; SUBSTRATES;

GATE BIAS; PROCESS SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0034454653     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. RF CMOS modelling
2. Impact of scaling down on Iow frequency noise in silicon MOS transistors
3. Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures
4. A physics-based MOSFET noise model for circuit simulators
5. Influence of fluorinated gate oxides on the low frequency noise of MOS transistors under analog operation
6. Modeling 1/f noise and extraction of the spice noise parameters using a new extraction procedure
7. Improvement of 1/f noise by using VHP oxynitride gate insulator for deep-sub micron RF and analog CMOS