Unified 1/f noise SOI MOSFET modelling for circuit simulation

Electronics Letters

Volumn 33, Issue 21, 1997, Pages 1781-1782

  Iniguez B ^a   Tambani, M ^b   Dessard, V ^b   Flandre, D ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Circuit noise; MOS integrated circuits; Silicon on insulator

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MODELS; SIGNAL NOISE MEASUREMENT; SILICON ON INSULATOR TECHNOLOGY;

ANALOGUE INTEGRATED CIRCUITS;

MOSFET DEVICES;

EID: 0031561256     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19971196     Document Type: Article

References (6)

1. TSIVIDIS, Y.: 'Operation and modelling of the MOS Transistor' (McGraw Hill, 1987)
2. GHIBAUDO, G.: 'Analytical modelling of the MOS transistor', Phys. Status Solidi, 1989, 113, pp. 223-239
3. GHIBAUDO, G., ROUX, O., NGUYEN-DUC, C., BALESTRA, F., and BRINI, J.: 'Improved analysis of low frequency noise in field-effect MOS transistor', Phys. Status Solidi, 1991, 124, pp. 571-580
4. HAFEZ, I.M., GHIBAUDO, G., and BALESTRA, F.: 'Flicker noise in metal-oxide-semiconductor transistors from liquid helium to room temperature', J. Appl Phys., 1989, 66, (5), pp. 2211-2213
5. FLANDRE, D., FERREIRA, L.F., JESPERS, P.G.A., and COLINGE, J.P.: 'Modelling and application of fully-depleted SOI MOSFETs for low-voltage low-power analogue CMOS circuits', Solid-State Electron., 1996, 39, pp. 455-460
6. ∞-continuous fully-depleted SOI MOSFET model for analogue applications', IEEE Trans. Electron. Devices, 1996, 43, (4), pp. 568-575