Comparison between matching parameters and fluctuations at the wafer level

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2002, Pages 241-246

  Difrenza, R ^a,b   Llinares, P ^a   Taupin, S ^a   Palla, S ^a   Palla, R ^a   Garnier, R ^a   Ghibaudo, G ^b  

^a STMICROELECTRONICS   (France)

^b Grenoble INP Phelma   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; MOSFET DEVICES; PHOTOLITHOGRAPHY; POLYSILICON; RANDOM PROCESSES; RESISTORS; SILICON WAFERS; SURFACE ROUGHNESS;

MATCHING PARAMETERS; POLYSILICON RESISTORS; RANDOM LOCAL FLUCTUATIONS;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0038495562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. P. Tuinhout et al., IEDM 1997, pp. 631-634.
2. A. Asenov et al., IEEE Trans. Electron Devices, vol. 47, 2000, pp. 805-812.
3. R. Difrenza et al., ESSDERC 2001, pp. 299-302.
4. T. Mizuno et al., IEEE Trans. Electron Devices, vol. 41, 1994, p. 2216-2221.
5. J. Bastos et al., IEEE Analog Integrated Circuits and Signal Processing, vol. 12, 1997.
6. Difrenza et al., ESSDERC 2000, pp 584-588.
7. Difrenza et al., to be published (ULIS 2002).