A CAD methodology for optimizing transistor current and sizing in analog CMOS design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 2, 2003, Pages 225-237

  Binkley, D M ^a   Hopper, C E ^a   Tucker, S D ^a   Moss, B C ^a,b   Rochelle, J M ^c   Foty, D P ^d  

^a University of North Carolina at Charlotte   (United States)

^b ANALOG DEVICES INC   (United States)

^c Concorde Microsystems Inc ^*  (United States)

^d Gilgamesh Associates   (United States)

Author keywords

DC mismatch; Intrinsic bandwidth; Intrinsic gain; Moderate and strong inversion; MOS and CMOS sizing; MOS and CMOS transconductance efficiency; Optimization methodology for analog MOS and CMOS design; Output conductance; Weak; White and flicker noise

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; OPTIMIZATION; TRANSCONDUCTANCE; WHITE NOISE;

CIRCUIT TRANSCONDUCTANCE; DRAIN CURRENT; FLICKER NOISE; TRANSISTOR CURRENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037318923     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.806606     Document Type: Article

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