Review of SiGe HBTs on SOI

Solid-State Electronics

Volumn 49, Issue 9 SPEC. ISS., 2005, Pages 1556-1567

  Mitrovic, I Z ^a   Buiu, O ^a   Hall, S ^a   Bagnall, D M ^b   Ashburn, P ^b  

^a UNIVERSITY OF LIVERPOOL   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

1 f noise; Bonded SOI wafers; Buried silicide layers; Lateral bipolar transistors (LBTs); SiGe heterojunction bipolar transistor (SiGe HBT); Silicon on insulator (SOI)

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ELASTICITY; FREQUENCIES; HETEROJUNCTION BIPOLAR TRANSISTORS; HIGH TEMPERATURE EFFECTS; SIGNAL PROCESSING; SILICON ON INSULATOR TECHNOLOGY;

1/F NOISE; BONDED SI WAFERS; BURIED SILICIDE LAYERS; LATERAL BIPOLAR TRANSISTORS; SIGE HETEROJUNCTION BIPOLAR TRANSISTORS (SIGE HBT); SILICON-ON-INSULATOR (SOI);

SILICON COMPOUNDS;

EID: 25844432314     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.07.020     Document Type: Conference Paper

References (92)

1. T SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications IEEE IEDM Tech Dig 1999 569 572
2. max and 6.7-ps ECL IEEE IEDM Tech Dig 1999 557 560
3. max) HBT and ASIC-compatible CMOS using copper interconnect. In: Proc BCTM, 2001. p. 143-6.
4. MAX SiGe technology IEEE ED Lett 23 2002 541 543
5. J.-S. Rieh, B. Jagannathan, H. Chen, K.T. Schonenberg, D. Angell, and A. Chinthakindi SiGe HBTs with cut-off frequency of 350 GHz IEEE IEDM Tech Dig 2002 771 774
6. max = 375 GHz/210 GHz. In: Proceedings of the international conference on indium phosphide and related materials, 2003. p. 374-7.
7. S. Zhang, G. Niu, J.D. Cressler, A.J. Joseph, G. Freeman, and D.L. Harame The effects of geometrical scaling on the frequency response and noise performance of SiGe HBTs IEEE Trans ED 49 2002 429 435
8. J.A. Johansen, Z. Jin, J.D. Cressler, Y. Cui, G. Niu, and Q. Liang On the scaling limits of low-frequency noise in SiGe HBTs Solid-State Electron 48 2004 1897 1900
9. Konig U. SiGe and GaAs as competitive technologies for RF-applications. In: Proceedings of BCTM, 1998. p. 87-92.
10. K. Washio SiGe HBT and BiCMOS technologies IEEE IEDM Tech Dig 2003 113 116
11. T of 350 GHz. In: IEEE Int 41st annual reliability physics symp proc, 2003. p. 332-8.
12. L.D. Lanzerotti, J.C. Sturm, E. Stach, R. Hull, T. Buyuklimanli, and C. Magee Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation IEEE IEDM Tech Dig 1996 249 252
13. I.M. Anteney, G. Lippert, P. Ashburn, H.J. Osten, B. Heinemann, and G.J. Parker Characterization of the effectiveness of carbon incorporation in SiGe for the elimination of parasitic energy barriers in SiGe HBT's IEEE ED Lett 20 1999 116 118
14. D.L. Harame, S.J. Koester, G. Freeman, P. Cottrel, K. Rim, and G. Dehlinger The revolution in SiGe: impact on device electronics Appl Surf Sci 224 2004 9 17
15. D.J. Paul Si/SiGe heterostructures: from material and physics to devices and circuits Semicond Sci Technol 19 2004 R76 R108
16. Martinet B, Baudry H, Kermarrec O, Campidelli Y, Laurens M, Marty M, et al. 100 GHz SiGe:C HBTs using non-selective base epitaxy. In: Proc ESSDERC, 2001. p. 97-100.
17. V.D. Kunz, C.H. de Groot, S. Hall, and P. Ashburn Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs IEEE Trans ED 50 2003 1480 1486
18. H. Rucker, B. Heinemann, R. Barth, D. Bolze, J. Drews, and U. Haak SiGe: BiCMOS technology with 3.6 ps gate delay IEEE IEDM Tech Dig 2003 121 124
19. B. Jagannathan, M. Meghelli, K. Chan, J.-S. Rieh, K. Schonenberg, and D. Ahlgren 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay IEEE ED Lett 24 2003 324 326
20. H. Knapp, M. Wurzer, T.F. Meister, K. Aufinger, J. Bock, and S. Boguth 86 GHz static and 110 GHz dynamic frequency dividers in SiGe bipolar technology IEEE MTT-S Int Microwave Symp Digest 2 2003 1067 1070
21. A. Rylyakov, L. Klapproth, B. Jagannathan, and G. Freeman 100 GHz dynamic frequency divider in SiGe bipolar technology Electron Lett 39 2003 217 218
22. F. Sato, T. Hashimoto, H. Fujii, H. Yoshida, H. Suzuki, and T. Yamazaki A 0.18-μm RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs IEEE Trans ED 50 2003 669 675
23. D.L. Harame, and B.S. Meyerson The early history of IBMs SiGe mixed signal technology IEEE Trans ED 48 2001 2555 2567
24. Chai FK, Reuter R, Baker T, Zupac D, Kirchgessner J. Outstanding noise characteristics of SiGe:C HBT allow flexibility in high-frequency RF designs. In: IEEE radio frequency integrated circuits (RFIC) Symp, 2003. p. 151-4.
25. W. Winkler, J. Borngräber, B. Heinemann, H. Rücker, R. Barth, and J. Bauer Circuit applications of high-performance SiGe:C HBTs integrated in BiCMOS technology Appl Surf Sci 224 2004 297 305
26. T SiGe:C bipolar RF technology. In: Topical meeting on silicon monolithic integrated circuits in RF systems, Digest of Papers, 2003. p. 10-3.
27. M.W. Xu, S. Decoutere, A. Sibaja-Hernandez, K. Van Wicheten, L. Witters, and R. Loo Ultra low power SiGe:C HBT for 0.18 μm RF-BiCMOS IEEE IEDM Tech Dig 2003 125 128
28. Baudry H, Martinet B, Fellous C, Kermarrec O, Campidelli Y, Laurens M, et al. High performance 0.25 μm SiGe and SiGe:C HBTs using non selective epitaxy. In: Proc BCTM, 2001. p. 52-5.
29. ett CMOS. In: Proc BCTM, 1999. p. 117-20.
30. T SiGe technology IEEE J Solid-State Circ 37 9 2002 1106 1114
31. T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, and M. Arai Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS IEEE IEDM Tech Dig 2003 129 132
32. G.K. Celler, and S. Cristoloveanu Frontiers of silicon-on-insulator J Appl Phys 93 9 2003 4955 4978
33. J.P. Colinge Silicon-on-insulator technology: materials to VLSI second ed. 1997 Kluwer Boston
34. Gamble HS. Variants on bonded SOI for advanced ICs. In: Cristoloveanu S, Hemment PLF, Izumi K, Celler GK, Assaderaghi F, Kim Y-W, editors. Silicon-on-insulator technology and devices X, Electrochemical Soc Proc; 2001-3. p. 1-12.
35. Plouchart J-O. SOI nano-technology for high-performance system on-chip applications. In: Proc IEEE Int SOI Conf, 2003. p. 1-4.
36. J.R. Schwank Advantages and limitations of SOI technology in radiation environments Microelectron Eng 36 1997 335 342
37. Feindt S, Lapham J, Steigerwals J. Complementary bipolar processes on bonded SOI. In: Proc IEEE Int SOI Conf, 1997. p. 4-6.
38. A. Watanabe, T. Nagano, S. Shukuri, and T. Ikeda Future BiCMOS technology for scaled supply voltage IEEE IEDM Tech Dig 1989 429 432
39. 2 CMOS memory cells for ECL-CMOS SRAM application IEEE IEDM Tech Dig 1992 39 42
40. Ueno S, Watanabe K, Kato T, Shinohara T, Mikami K, Hashimoto T, et al. A single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS. IEEE Tech Dig Int Solid-State Circuits Conf (ISSCC), 2001. p. 82-3.
41. Nishizawa H, Azuma S, Yoshitake T, Masuda H, Kawaji M, Anzai A. An advanced dielectric isolation structure for SOI-CMOS/BiCMOS VLSI's. In: Proceedings of 2nd international symposium on semiconductor wafer bonding: science, technology and applications, The Electrochemical Society 1993; PV93-29. p. 176-88.
42. L.J. McDaid, S. Hall, P.H. Mellor, W. Eccleston, and J.C. Alderman Physical origin of negative differential resistance in SOI transistors IEE Electron Lett 25 13 1989 827 828
43. J. Olsson Self-heating effects in SOI bipolar transistors Microelectron Eng 56 2001 339 352
44. S. Stefanou, J.S. Hamel, P. Baine, M. Bain, B.M. Armstrong, and H.S. Gamble Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology IEEE Trans ED 51 2004 486 491
45. M. Mastrapasqua, P. Palestri, A. Pacelli, G.K. Celler, M.R. Frei, and P.R. Smith Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI IEEE Trans ED 23 2002 145 147
46. x HBTs on bulk-Si and SOI substrates. In: Proc BCTM, 2001. p. 98-101.
47. T. Vanhoucke, H.M.J. Boots, and W.D. van Noort Revised method for extraction of the thermal resistance applied to bulk and SOI SiGe HBTs IEEE ED Lett 25 2004 150 152
48. Haralson E, Malm BG, Johansson T, Ostling M. Influence of self heating in a BiCMOS on SOI technology. In: Proc ESSDERC, 2004. p. 337-40.
49. Cai J, Kumar M, Steigerwalt M, Ho H, Schonenberg K, Stein K, et al. Vertical SiGe base bipolar transistors on CMOS compatible SOI substrates. In: Proc BCTM, 2003. p. 215-8.
50. max 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications IEEE Trans ED 49 2002 271 278
51. T super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter IC's IEEE Trans ED 46 1999 1332 1338
52. Cai J, Ajmera A, Ouyang C, Oldiges P, Steigerwalt M, Stein K, et al. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI. In: Tech Dig Symp VLSI Technol, 2002. p. 172-3.
53. S. Hall, A.C. Lamb, M. Bain, B.M. Armstrong, H. Gamble, and H.A.W. El Mubarek SiGe HBTs on bonded wafer substrates Microelectron Eng 59 2001 449 454
54. J.-P. Raskin, A. Viviani, D. Flandre, and J.P. Colinge Substrate crosstalk reduction using SOI technology IEEE Trans ED 44 1997 2252 2261
55. J.S. Hamel, S. Stefanou, M. Bain, B.M. Armstrong, and H.S. Gamble Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI) IEEE Microwave Guided Wave Lett 10 1 2000 134 135
56. T. Nakamura, and H. Nishizawa Recent progress in bipolar transistor technology IEEE Trans ED 42 1995 390 398
57. Ashburn P, El Mubarek HAW, Bonar JM, Redman-White W. SiGe heterojunction bipolar transistors on insulator. In: Cristoloveanu S, Hemment PLF, Izumi K, Celler GK, Assaderaghi F, Kim Y-W, editors. Silicon-on-insulator technology and devices X, Electrochemical Soc Proc; 2001-3. p. 433-44.
58. S. Hall, O. Buiu, I.Z. Mitrovic, H.A.W. El Mubarek, P. Ashburn, and M. Bain SiGe heterojunction bipolar transistors on insulating substrates D. Flandre Science and technology of semiconductor-on-insulator structures and devices operating in a harsh environment 2005 Kluwer Academic Publishers 261 272
59. F. Sato, T. Hashimoto, T. Tatsumi, and T. Tashiro Sub-20 ps ECL circuits with high-performance super self-aligned selectively grown SiGe base (SSSB) bipolar transistors IEEE Trans ED 42 1995 483 488
60. Sugiyama M, Shimizu T, Takemura H, Yoshino A, Oda N, Tashiro T, et al. Bipolar VLSI memory cell technology utilizing BPSG-filled trench isolation. In: Tech Dig Symp VLSI Technol, 1989. p. 59-60.
61. M. Bain, H.A.W. El Mubarek, J.M. Bonar, Y. Wang, O. Buiu, and H. Gamble SiGe HBTs on bonded SOI incorporating buried silicide layers IEEE Trans ED 52 2005 317 324
62. H.A.W. El Mubarek, J.M. Bonar, P. Ashburn, Y. Wang, P.L.F. Hemment, and O. Buiu Non-selective growth of SiGe heterojunction bipolar transistor layers at 700 °C with dual control of n- and p-type dopant profiles J Mater Sci: Mater Electron 14 5-7 2003 261 265
63. J.F.W. Schiz, A.C. Lamb, F. Cristiano, J.M. Bonar, P. Ashburn, and S. Hall Leakage current mechanisms in SiGe HBTs fabricated using selective and nonselective epitaxy IEEE Trans ED 48 2001 2492 2499
64. J.M. Bonar, J.F.W. Schiz, and P. Ashburn Selective and non-selective growth of self-aligned SiGe HBT structures by LPCVD epitaxy J Mater Sci: Mater Electron 10 1999 345 349
65. N. Lukyanchikova, N. Garbar, A. Smolanka, M. Lokshin, S. Hall, and O. Buiu 1/f noise and generation/recombination noise in SiGe HBTs on SOI IEEE Trans ED 52 2005 1468 1477
66. Hall S, Buiu O, Lamb AC, El Mubarek HAW, Ashburn P. Current crowding effects in SOI-SiGe HBT's with low doped emitters. In: Proc ESSDERC, 2003. p. 303-6.
67. N.B. Lukyanchikova Noise research in semiconductor physics 1996 Gordon & Breach Publishers [chapter 5]
68. W.L. Goh, S.H. Raza, J.H. Montgomery, B.M. Armstrong, and H.S. Gamble Manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers IEEE ED Lett 20 1999 212 214
69. x SOI structures. In: Proceedings of IEEE international SOI conference, 1995. p. 137-8.
70. Zhu S, Ru G, Huang Y. Fabrication of silicon-silicide-on-insulator substrates using wafer bonding and layer cutting. In: Proceedings of 6th international conference on solid state and integrated circuit technology, 2001. p. 673-5.
71. H.S. Gamble, B.M. Armstrong, P. Baine, M. Bain, and D.W. McNeill Silicon-on-insulator substrates with buried tungsten silicide layer Solid-State Electron 45 2001 551 557
72. x ground planes IEEE ED Lett 26 2005 72 74
73. R. Gomez, R. Bashir, and G.W. Neudeck On the design and fabrication of novel lateral bipolar transistor in a deep-submicron technology Microelectron J 31 2000 199 205
74. max on thin-film SOI for RF analog applications IEEE Trans ED 47 2000 1536 1541
75. B. Edholm, J. Olsson, and A. Soderbarg A self-aligned lateral bipolar transistor realized on SIMOX-material IEEE Trans ED 40 1993 2359 2360
76. M. Rodder, and D.A. Antoniadis Silicon-on-insulator bipolar transistors IEEE ED Lett 4 1983 193 195
77. T.I. Kamins, and D.R. Bradbury Trench-isolated transistors in lateral CVD epitaxial silicon-on-insulator films IEEE ED Lett 5 1984 449 451
78. J.P. Colinge Half-micrometer-base lateral bipolar transistors made in thin-silicon-on-insulator films IEE Electron Lett 22 17 1986 886 887
79. J.C. Sturm, J.P. McVittie, J.F. Gibbons, and L. Pfeiffer A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact IEEE ED Lett 8 1987 104 106
80. S.A. Parke, C. Hu, and P.K. Ko A high-performance lateral bipolar transistor fabricated on SIMOX IEEE ED Lett 14 1993 33 35
81. G.G. Shahidi, D.D. Tang, B. Davari, Y. Taur, P. McFarland, and K. Jenkins A novel high-performance lateral bipolar on SOI IEEE IEDM Tech Dig 1991 663 666
82. R. Dekker, W.T.A. v.d. Einden, and H.G.R. Maas An ultra low power lateral bipolar polysilicon emitter technology on SOI IEEE IEDM Tech Dig 1993 75 78
83. J.A. Babcock, W.M. Huang, J.M. Ford, D. Ngo, D.J. Spooner, and S. Cheng Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-mode applications IEEE IEDM Tech Dig 1996 133 136
84. max lateral BJT on SOI using self-aligned external base formation technology IEEE IEDM Tech Dig 1998 953 956
85. T. Shino, S. Yoshitomi, H. Nii, S. Kawanaka, K. Inoh, and T. Yamada Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications IEEE Trans ED 49 2002 414 421
86. W.-L.M. Huang, K.M. Klein, M. Grimaldi, M. Racanelli, S. Ramaswami, and J. Tsao TFSOI complementary BiCMOS technology for low power applications IEEE Trans ED 42 1995 506 512
87. Tang YT. Advance characterisation and modelling of SiGe HBT's. PhD thesis, University of Southampton, 2000.
88. Osman K. Fabrication of lateral silicon germanium heterojunction bipolar transistors. PhD thesis, University of Southampton, 2003.
89. Hamel JS, Tang YT. Numerical simulation and comparison of vertical and lateral SiGe HBT's for RF/microwave applications. In: Proc ESSDERC, 2000. p. 620-3.
90. P.J. Schubert, and G.W. Neudeck Confined lateral selective epitaxial growth of silicon for device fabrication IEEE ED Lett 11 1990 181 183
91. P. Pengpad, K. Osman, N.S. Lloyd, J.M. Bonar, P. Ashburn, and H.A. Kemhadjian Lateral SiGe heterojunction bipolar transistor by confined selective epitaxial growth: simulation and material growth Microelectron Eng 73-74 2004 508 513
92. J.S. Hamel, Y.T. Tang, and K. Osman Technological requirements for a lateral SiGe HBT technology including theoretical performance predictions relative to vertical SiGe HBTs IEEE Trans ED 49 2002 449 456