Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 129-132

  Hashimoto, Takashi ^a   Nonaka, Yusuke ^a   Tominari, Tatsuya ^a   Fujiwara, Hiroaki ^a   Tokunaga, Kazuaki ^a   Arai, Mitsuru ^a   Wada, Shinichiro ^a   Udo, Tsutomu ^a   Seto, Motoshi ^a   Miura, Makoto ^a   Shimamoto, Hiromi ^a   Washio, Katsuyoshi ^a   Tomioka, Hideki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CURRENT DENSITY; ELECTRIC BREAKDOWN; EMITTER COUPLED LOGIC CIRCUITS; EPITAXIAL GROWTH; HETEROJUNCTION BIPOLAR TRANSISTORS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; RAPID THERMAL ANNEALING; SEMICONDUCTOR DOPING; SILICON COMPOUNDS;

EMITTER-WIDTH SCALING EFFECT; THERMAL BUDGETS;

CMOS INTEGRATED CIRCUITS;

EID: 0842331408     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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7. 2 6-T SRAM Cell", IEDM Techn. Digest, pp. 73-76, 2002.
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9. D. T. Zweidinger et al., "Thermal Impedance Extraction for Bipolar Transistors", IEEE Trans. Electron Devices, pp.342-346, February 1996.