Substrate Crosstalk Suppression Capability of Silicon-on-Insulator Substrates with Buried Ground Planes (GPSOI)

IEEE Microwave and Guided Wave Letters

Volumn 10, Issue 4, 2000, Pages 134-135

  Hamel, J S ^a   Stefanou, S ^a   Bain, M ^b   Armstrong, B M ^b   Gamble, H S ^b  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CROSSTALK; INTERFERENCE SUPPRESSION; OXIDES;

GROUND PLANE SILICON-ON-INSULATOR (GPSOI) TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0034171745     PISSN: 10518207     EISSN: None     Source Type: Journal    
DOI: 10.1109/75.846923     Document Type: Article

References (2)

1. J. Raskin, A. Viviani, D. Flandre, and J. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Trans. Electron Devices, vol. 44, pp. 2252-2261, Dec. 1997.
2. W. Goh, D. Campbell, B. Armstrong, and H. Gamble, “Buried metallic layers with silicon direct bonding,” Spring Meeting of the Electrochem. Soc., vol. 95-97, pp. 553-560, May 1995.