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Volumn 51, Issue 3, 2004, Pages 486-491

Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology

Author keywords

Faraday cage; Integrated circuit noise; Microwave devices; S parameters; Silicon on insulator (SOI); Substrate crosstalk

Indexed keywords

ANTENNAS; ASPECT RATIO; CAPACITANCE; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; FARADAY EFFECT; FREQUENCIES; INTEGRATED CIRCUITS; MICROMACHINING; MICROWAVE DEVICES; SCATTERING PARAMETERS; SPURIOUS SIGNAL NOISE;

EID: 1642306308     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.822348     Document Type: Article
Times cited : (33)

References (11)
  • 1
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    • (1994) IEEE J. Solid-state Circuits , vol.29 , pp. 1212-1219
    • Joardar, K.1
  • 4
    • 0034171745 scopus 로고    scopus 로고
    • Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)
    • Apr.
    • J. Hamel, S. Stefanou, M. Bain, B. Armstrong, and H. Gamble, "Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)," IEEE Microwave Guided Waves Lett., vol. 10, pp. 134-135, Apr. 2000.
    • (2000) IEEE Microwave Guided Waves Lett. , vol.10 , pp. 134-135
    • Hamel, J.1    Stefanou, S.2    Bain, M.3    Armstrong, B.4    Gamble, H.5
  • 9
    • 0032649563 scopus 로고    scopus 로고
    • The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers
    • May
    • W. Goh, J. Montgomery, S. Raza, B. Armstrong, and H. Gamble, "The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers," IEEE Electron Device Lett., vol. 20, pp. 212-214, May 1999.
    • (1999) IEEE Electron Device Lett. , vol.20 , pp. 212-214
    • Goh, W.1    Montgomery, J.2    Raza, S.3    Armstrong, B.4    Gamble, H.5
  • 10
    • 0035694018 scopus 로고    scopus 로고
    • Physics and compact modeling of SOI substrates with buried ground plane (GPSOI) for substrate noise suppression
    • May
    • S. Stefanou, J. Hamel, M. Bain, B. Armstrong, H. Gamble, R. Mauntel, and M. Huang, "Physics and compact modeling of SOI substrates with buried ground plane (GPSOI) for substrate noise suppression," in IEEE Int. Microwave Symp. Dig., May 2001, pp. 1877-1880.
    • (2001) IEEE Int. Microwave Symp. Dig. , pp. 1877-1880
    • Stefanou, S.1    Hamel, J.2    Bain, M.3    Armstrong, B.4    Gamble, H.5    Mauntel, R.6    Huang, M.7
  • 11
    • 0032075292 scopus 로고    scopus 로고
    • On-chip spiral inductors with patterned ground shields for Si-based RF ics
    • May
    • C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ics," IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 743-752
    • Yue, C.P.1    Wong, S.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.