Lateral SiGe heterojunction bipolar transistor by confined selective epitaxial growth: Simulation and material growth

Microelectronic Engineering

Volumn 73-74, Issue , 2004, Pages 508-513

  Pengpad, P ^a   Osman, K ^a   Lloyd, N S ^a   Bonar, J M ^a   Ashburn, P ^a   Kemhadjian, H A ^a   Hamel, J S ^b   Bagnall, D M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Confined lateral selective epitaxial growth; Heterojunction bipolar transistor; SiGe; SiGe HBT device simulation; SiGe HBT process simulation

Indexed keywords

COMPUTER SIMULATION; EPITAXIAL GROWTH; FREQUENCIES; LITHOGRAPHY; SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

CONFINED LATERAL SELECTIVE EPITAXIAL GROWTH; SIGE; SIGE HBT DEVICE SIMULATION; SIGE HBT PROCESS SIMULATION;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 2542442017     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(04)00202-3     Document Type: Conference Paper

References (10)

1. J.S. Rieh, B. Jagannathan, H. Chen, K.T. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S.J. Jeng, M. Khater, F. Pagette, C. Schnabel, P. Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, S. Subbanna, in: IEEE International Electron Devices Meeting, 8-11 December 2002, San Francisco, CA, USA, 2002.
2. Schubert P.J., Neudeck G.W. IEEE Electron Device Lett. 11:1990;181-183.
3. Hamel J.S., Tang Y.T., Osman K. IEEE Trans. Electron Devices. 49:2002;449-456.
4. K. Osman, N.S. Lloyd, J.S. Hamel, J.M. Bonar, H.A. Kemhadjian, D.M. Bagnall, in: The 4th International Conference on Materials for Microelectronics and Nanoengineering (MFMN 2002), Hanaasari Cultural Centre, Espoo, Finland, 2002.
5. ATHENA User's Manual, 2-D Process Simulation Software, 1996.
6. S. Decoutere, F. Vleugels, R. Kuhn, R. Loo, M. Caymax, S. Jenei, J. Croon, S. Van-Huylenbroeck, M. Da-Rold, E. Rosseel, P. Chevalier, P. Coppens, in: Bipolar/BiCMOS Circuits and Technology Meeting, 2000, Proceedings of the 2000, 24-26 September, 2000, pp. 106-109.
7. Washio K., Ohue E., Shimamoto H., Oda K., Hayami R., Kiyota Y., Tanabe M., Kondo M., Hashimoto T., Harada T. Electron Devices IEEE Trans. 49(2):2002;271-278.
8. T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, T. Yamazaki, in: Electron Devices Meeting, 2000, IEDM Technical Digest, International, 10-13 December, pp. 149-152, 2000.
9. ATLAS User's Manual, Device Simulation Software, Version 1.5.0, 1997.
10. T. Shino, K. Inoh, T. Yamada, H. Nii, S. Kawanaka, T. Fuse, M. Yoshimi, Y. Katsumata, S. Watanabe, J. Matsunaga, in: Electron Devices Meeting, 1998, IEDM '98 Technical Digest, International, 6-9 December, 1998, pp. 953-956.