SiGe HBTs on bonded SOI incorporating buried silicide layers

IEEE Transactions on Electron Devices

Volumn 52, Issue 3, 2005, Pages 317-324

  Bain, M ^a   El Mubarek, H A W ^b   Bonar, J M ^b   Wang, Y ^c   Buiu, O ^d   Gamble, H ^a   Armstrong, B M ^a   Hemment, Peter L F ^c   Hall, Steven ^d   Ashburn, Peter ^b  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^c UNIVERSITY OF SURREY   (United Kingdom)

^d UNIVERSITY OF LIVERPOOL   (United Kingdom)

Author keywords

Buried layer; Groundplane; SiGe heterojunction bipolar transistors (HBTs); Silicon on insulator (SOI); Tungsten silicide; Wafer bonding

Indexed keywords

ELECTRIC CONDUCTIVITY; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DIODES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES; TRANSMISSION ELECTRON MICROSCOPY; TUNGSTEN COMPOUNDS;

BURIED GROUNDPLANE; BURIED LAYER; SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS; TUNGSTEN SILICIDE; WAFER BONDING;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 20144375967     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.843872     Document Type: Article

References (26)

1. D. L. Harame, J. H. Comfort, J. D. Cressler, E. F. Crabbé, J. Y.-C. Sun, B. S. Meyerson, and T. Tice, "Si-SiGe epitaxial base transistors - Part I: Materials, physics, and circuits," IEEE Trans. Electron Devices, vol. 42, no., pp. 455-467, Apr. 1995.
2. D. L. Harame, J. H. Comfort, J. D. Cressler, E. F. Crabbé, J. Y.-C. Sun, B. S. Meyerson, and T. Tice, "Si-SiGe epitaxial base transistors - Part II: process integration and analog applications," IEEE Trans. Electron Devices, vol. 42, no. 4, pp. 469-482, Apr. 1995.
3. J. Böck, T. F. Meister, H. Knapp, D. Zöchg, H. Schäfer, K. Aufinger, M. Wurzer, S. Boguth, M. Franosch, R. Stengl, R. Schreiter, M. Rest, and L. Treitinger, "SiGe bipolar technology for mixed digital and analogue RF applications," in IEDM Tech. Dig., 2000, pp. 745-748.
4. max and 6.7 ps ECL," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 1989-1994, Dec. 2001.
5. B. Martinet, H. Baudry, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, T. Schwartzmann, A. Monroy, D. Bensahel, and A. Chantre, "100 GHz SiGe: C HBTs using nonselective epitaxy," in Proc. Eur. Solid-State Device Research Conf., 2001, pp. 97-100.
6. T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, and T. Yamazaki, "A 73 GHz fT 0.18 μm RF SiGe BiCMOS technology considering thermal budget tradeoff and with reduced boron spike effect on HBT tics," in IEDM Tech. Dig., 2000, pp. 149-152.
7. J. N. Burghartz, M. Soyuer, K. A. Jenkins, M. Kies, M. Dolan, K. J. Stein, J. Malinowski, and D. L. Harame, "Integrated RF components in a SiGe BiCMOS technology," IEEE J. Solid-State Circuits, vol. 32, pp. 1440-1445, 1997.
8. A. Schüppen, "SiGe HBTs for mobile communication," Solid State Electron., vol. 43, pp. 1373-1381, 1999.
9. T in a manufacturable technology," IEEE Electron Device Lett., no. 5, pp. 255-258, May 2002.
10. K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, T. Masuda, K. Ohhata, and M. Kondo, "Self-aligned selective-epitaxial-growth SiGe HBTs: process, device, and ICs," Thin Solid Films, vol. 369, pp. 352-357, 2000.
11. M. Suzaki, M. Soda, T. Morikawa, H. Tezuka, C. Ogawa, S. Fujita, H. Takemura, and T. Tashiro, "Si bipolar chip set for 10-Gb/s optical receiver," IEEE J. Solid State Circuits, vol. 27, pp. 1781-1786, 1992.
12. M. Soda, H. Tezuka, F. Sato, T. Hashimoto, S. Nakamura, T. Tatsumi, T. Suzaki, and T. Tashiro, "Si-analog ICs for 20 Gb/s optical receiver," in Proc. ISSCC Tech. Dig., 1994, pp. 170-173.
13. H. M. Rein and M. Möller, "Design considerations for very-high-speed Si-bipolar ICs operating up to 50 Gb/s," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1076-1090, Nov. 1996.
14. R. Schmid, T. F. Meister, M. Rest, and H. M. Rein, "40 Gbit/s EAM driver IC in SiGe bipolar technology," Electron. Lett., vol. 34, pp. 1095-1096, 1998.
15. T. Nakamura and H. Nishizawa, "Recent progress in bipolar transistor technology," IEEE Trans. Electron Devices, vol. 42, no. 3, pp. 390-398, Mar. 1995.
16. T super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs," IEEE Trans. Electron Devices., vol. 46, no. 12, pp. 1332-1338, Dec. 1999.
17. S. Hall, A. C. Lamb, M. Bain, B. M. Armstrong, H. Gamble, H. A. W. El Mubarek, and P. Ashburn, "SiGe HBTs on bonded wafer substrates," Microelectron. Eng., vol. 59, pp. 449-454, 2001.
18. max 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications," IEEE Trans. Electron Devices, vol. 49, no. Feb., pp. 271-278, 2002.
19. J. Cai, M. Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K. Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Oldiges, and T. Ning, "Vertical SiGe base bipolar transistors on CMOS compatible SOI substrates," in Proc. BCTM, 2003, pp. 215-218.
20. J. S. Hamel, S. Stefanou, M. Bain, B. M. Armstrong, and H. S. Gamble, "Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)," IEEE Microw. Guided Wave Lett., vol. 10, no. 1, pp. 134-135, Jan. 2000.
21. S. Stefanou, J. S. Hamel, P. Baine, M. Bain, B. M. Armstrong, H. S. Gamble, M. Kraft, and H. A. Kemhadjian, "Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 486-491, Mar. 2004.
22. W. L. Goh, S. H. Raza, J. H. Montgomery, B. M. Armstrong, and H. S. Gamble, "Manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers," IEEE Electron Device Lett., vol. 20, no. 5, pp. 212-214, May 1999.
23. x SOI structures," in Proc. SOI Conf., 1995, pp. 137-138.
24. S. Zhu, G. Ru, and Y. Huang, "Fabrication of silicon-silicide-on-insulator substrates using wafer bonding and layer cutting," in Proc. 6th Int. Conf. Solid State and Integrated Circuit Technologies, 2001, pp. 673-675.
25. J. F. W. Schiz, A. C. Lamb, F. Cristiano, J. M. Bonar, P. Ashburn, S. Hall, and P. L. F. Hemment, "Leakage current mechanisms in SiGe heretojunction bipolar transistors fabricated using selective and nonselective epitaxy," IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2492-2499, Nov. 2001.
26. M. F. Bain, N. D. McCusker, P. McCann, W. A. Nevin, and H. S. Gamble, "Back-end analysis of SOI substrates incorporating metallic layers using a novel nondestructive picosecond ultrasonic technique," in Proc. Electrochemical Society, vol. 5, Silicon on Insulator Technology and Devices XI, Apr. 2003, pp. 63-68.