Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

IEEE Electron Device Letters

Volumn 23, Issue 3, 2002, Pages 145-147

  Mastrapasqua, Marco ^a,b   Palestri, P ^b   Pacelli, Andrea ^a,c   Celler, George K ^a,b,d   Frei, M R ^b   Smith, P R ^b   Johnson, R W ^b   Bizzarro, L ^b   Lin, W ^a,b   Ivanov, Tony G ^a,b   Carroll, Michael S ^a,b   Kizilyalli, Isik C ^a,b   King, C A ^b  

^a IEEE   (United States)

^b AGERE SYSTEMS   (United States)

^c Stony Brook University   (United States)

^d Soitec USA   (United States)

Author keywords

Bipolar; Germanium; Silicon; SOI

Indexed keywords

HIGH ENERGY IMPLANTATION (HEI);

CAPACITANCE; CMOS INTEGRATED CIRCUITS; HEAT RESISTANCE; SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

BIPOLAR TRANSISTORS;

EID: 0036503662     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.988819     Document Type: Article

References (10)

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3. T of 80 GHz
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5. Integration of high-Q inductors in a latch-up resistant CMOS technology
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7. x HBT's on bulk-Si and SOI substrates
8. x HBTs
9. A merged 2.5 V and 3.3 V 0.25 μm CMOS technology for ASICs