SiGe:C BiCMOS Technology with 3.6 ps Gate Delay

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 121-124

  Rucker H ^a   Heinemann, B ^a   Barth, R ^a   Bolze, D ^a   Drews, J ^a   Haak, U ^a   Hoppner W ^a   Knoll, D ^a   Kopke K ^a   Marschmeyer, S ^a   Richter, H H ^a   Schley, P ^a   Schmidt, D ^a   Scholz, R ^a   Tillack, B ^a   Winkler, W ^a   Wulf, H E ^a   Yamamoto, Y ^a  

^a IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; HETEROJUNCTION BIPOLAR TRANSISTORS; SCANNING ELECTRON MICROSCOPY; SILICON COMPOUNDS;

BASE-COLLECTOR CAPACITANCE; GATE DELAYS;

CMOS INTEGRATED CIRCUITS;

EID: 0842331404     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. B. Jagannathan et al., "Self-Aligned SiGe NPN Technology with 285 GHz fmax and 207 GHz fT in a Manufacturante Technology", EDL 23, p. 258 (2002).
2. B. Heinemann et al., "Novel Collector Design for High-Speed SiGe:C HBTs", IEDM 2002, p.775.
3. B. Jagannathan et al., "A 4.2-ps ECL Ring-Oscillator in a 285-GHz fmax SiGe Technology", EDL 23, p. 541 (2002).
4. T. F. Meister et al., "SiGe Bipolar Technology with 3.9 ps Gate Delay", Program of BCTM 2003.
5. max InP DHBTs", Electronics Letters 39, p. 1215 (2003).