Substrate crosstalk reduction using SOI technology

IEEE Transactions on Electron Devices

Volumn 44, Issue 12, 1997, Pages 2252-2261

  Raskin, Jean Pierre ^a   Viviani, Alberto ^a   Flandre, Denis ^a   Colinge, Jean Pierre ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; SEMICONDUCTOR DEVICE MODELS; SUBSTRATES;

CAPACITIVE GUARD RINGS; SUBSTRATE CROSSTALK;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0031341419     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.644646     Document Type: Article

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