Scaling planar silicon devices

IEEE Circuits and Devices Magazine

Volumn 20, Issue 1, 2004, Pages 6-19

  Chuang, Ching Te ^a   Bernstein, Kerry ^a   Joshi, Rajiv V ^a   Puri, Ruchir ^a   Kim, Keunwoo ^a   Nowak, Edward J ^b   Ludwig, Thomas ^c   Aller, Ingo ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM MICROELECTRONICS   (United States)

^c IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; HYSTERESIS; NANOTECHNOLOGY; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

FULLY DEPLETED SILICON ON INSULATOR TECHNOLOGY; PARTIALLY DEPLETED SILICON ON INSULATOR TECHNOLOGY; PLANAR DEVICE STRUCTURES; PLANAR SILICON DEVICES; STRAINED SILICON;

SEMICONDUCTOR DEVICE TESTING;

EID: 1842865630     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2004.1263403     Document Type: Article

References (64)

1. H.-S.P. Wong, D.J. Frank, P.M. Solomon, H.J. Wann, and J. Welser, "Nanoscale CMOS," Proc. IEEE, vol. 87, no. 4, pp. 537-570, Apr. 1999.
2. L. Chang, Y.K. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu, and T.J. King, "Moore's law lives on," IEEE Circuits Devices Mag., vol. 23, pp. 35-42, Jan. 2003.
3. C.T. Chuang, P.F. Lu, and C.J. Anderson, "SOI for digital CMOS VLSI: Design considerations and advances," Proc. IEEE, vol. 86, no. 4, pp. 689-720, Apr. 1998.
4. M. Canada, et al., "A 580 RISC microprocessor in SOI," in Dig. Tech. Papers, ISSCC 1999, pp. 430-431.
5. D.H. Allen, et al., "A 0.20 (μm1.8 V SOI 550 MHz 64b PowerPC microprocessor with Cu interconnects," in Dig. Tech. Papers, ISSCC 1999, pp. 438-439.
6. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, Z. Ren, F.F. Jamin, L. Shi, W. Natzle, H.J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E.C. Jones, R.J. Miller, H.-S.P. Wong, and W. Haensch, "Extreme scaling with ultra-thin Si channel MOSFETs," in Tech. Digest, IEDM 2002, pp. 267-270
7. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA)," in Tech. Digest IEDM 1989, pp. 833-836.
8. S.-H. Tang, L. Chang, N. Lindert, Y.K. Choi, W.C. Lee, X. Huang, V. Subramanian, J. Bokor, T.J. King, and C. Hu, "FinFET-A quasi-planar double-gate MOSFET," in Digest Tech. Papers ISSCC 2001, pp. 118-119.
9. T asymmetric-gate FinFET devices," in Tech. Digest IEDM 2001, pp. 437-440.
10. B.H. Lee et al., "Performance enhancement on sub-70 nm strained Si MOS-FETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D," in Tech. Digest IEDM 2002 pp. 946-948.
11. P.F. Lu, C.T. Chuang, J. Ji, L.F. Wagner, C.M. Hsieh, J.B. Kuang, L. Hsu, M.M. Pelella, S. Chu, and C.J. Anderson, "Floating body effects in partially-depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, 32, no. 8, pp. 1241-1253, Aug. 1997.
12. C.T. Chuang, P.F. Lu, J. Ji, L.F. Wagner, S. Chu, and C.J. Anderson, "Dual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially-depleted SOI devices," in Proc. Tech. Papers, Int. Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1997, pp. 188-292.
13. C.T. Chuang and R. Puri, "SOI digital CMOS VLSI-A design perspective," in Proc. 36th Design Automation Conf., New Orleans, 1999, pp. 709-714
14. J.B. Kung, M.J. Saccamango, P.F. Lu, C.T. Chuang, and F. Assaderaghi, "A dynamic body discharge technique for SOI circuit applications," in Proc. IEEE Int. SOI Conf., 1999, pp. 77-78.
15. J.B. Kuang, D.H. Allen, and C.T. Chuang, "Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 597-604, April 2001.
16. J.B. Kuang and C.T. Chuang, "A tri-state body charge modulated SOI sense amplifier," in Proc. IEEE Int. SOI Conf., 2001, pp. 135-136.
17. A. Wei, D.A. Antoniadis, and L.A. Bair, "Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS," IEEE Elec. Dev. letters, vol. 17, no. 8, pp. 391-394, Aug. 1996.
18. T-variation in partially-depleted SOI CMOS," in Tech. Digest, IEDM 1997, pp. 411-414.
19. T.W. Houston and S. Unnikrishnan, "A guide to simulation of hysteretic gate delays based on physical understanding," in Proc. IEEE Int. SOI Conf., 1998, pp. 121-122.
20. M.M. Pelella, C.T. Chuang, C. Tretz, B.W. Curran, and M.G. Rosenfield, "Hysteresis in floating-body PD/SOI CMOS circuits," in Proc. Tech. Papers, Int. Symp. on VLSI Tech., Syst., and Applications, Taipei, Taiwan, 1999, pp. 278-281.
21. R. Puri and C.T. Chuang, "Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits," in Proc. Int. Symp. on Low Power Electronics and Design, 1999, pp. 223-228.
22. R. Puri and C.T. Chuang, "Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits," in Proc. IEEE Int. SOI Conf., 1998, pp. 103-104.
23. R. Puri and C.T. Chuang, "Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 625-631, April 2000.
24. K.A. Jenkins, R. Puri, C.T. Chuang, and F.L. Pesavento, "Measurement of history effect in PD/SOI single-ended CPL circuit," in Proc. IEEE Int. SOI Conf., 2001, pp. 57-58.
25. I. Aller, and K.E. Kroell, "Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits," in Proc. IEEE Int. SOI Conf., 1999, pp. 40-41.
26. K.L. Shepard and D.J. Kim, "Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," in Dig. Tech. Papers, IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 1999, pp. 531-538.
27. S.K.H. Fung, N. Zamdmer, P.J. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.H. Lo, R. Joshi, C.T. Chuang, I. Yang, S. Crowder, T.C. Chen, F. Assaderaghi, and G. Shahidi, "Controlling floating-body effects for 0.13 μm and 0.10 μm SOI CMOS," in Tech. Digest IEDM 2000, pp. 231-234.
28. P. Su, K. Goto, T. Sugii, and C. Hu, "Self-heating enhanced impact ionization in SOI MOSFETs," in Proc. IEEE Int. SOI Conf., 2001, pp. 31-32.
29. P. Su, S.K.H. Fung, H. Wan, A. Niknejad, M. Chan, and C. Hu, "An impact ionization model for SOI circuit simulation," in Proc. IEEE Int. SOI Conf., 2002, pp. 201-202.
30. E. Leobandung, et al., "Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation," in Tech. Digest IEDM 1998, pp. 403-406.
31. A. Vandooren, D. Jovanovic, S. Egley, M. Sadd, B.Y. Nguyen, B. White, M. Orlowski, and J. Mogab, "Scaling assessment of fully-depleted SOI technology at the 30 nm gate length generation," in Proc. IEEE Int. SOI Conf., 2002, pp. 25-27.
32. J.G. Fossum, V.P. Trivedi, and K. Wu, "Extremely scaled fully depleted SOI CMOS," in Proc. IEEE Int. SOI Conf., 2002, pp. 135-136.
33. T. Ghani, et al., "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Dig. of Tech. Papers, Symp. VLSI Technology, 2000, pp. 174-175.
34. E.J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down," IBM J. Res. & Develop., vol. 46, no. 2/3, pp. 169-180, March/May 2002.
35. W.C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction- and valance-band electron and hole tunneling," in Dig. of Tech. Papers, Symp. VLSI Technology, 2000, pp. 198-199.
36. C.T. Chuang, R. Puri, and K. Bernstein, "Effect of gate-to-body tunneling current on PD/SOI CMOS circuits," Extended Abstracts, Int. Conf. on Solid State Devices and Materials, Tokyo, Japan, 2001, pp. 262-263.
37. C.T. Chuang and R. Puri, "Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits," in Proc. IEEE Int. SOI Conf., 2002, pp. 121-122.
38. C.T. Chuang and R. Puri, "Effects of gate-to-body tunneling current on PD/SOI CMOS latches," in Proc. International Conf. Simulation of Semiconductor Processes and Devices (SISPAD'01), Cambridge, MA, Sept. 3-5, 2003, pp. 291-294.
39. R.V. Joshi, A. Pellela, O. Wagner, Y.H. Chan, W. Dachtera, S. Wilson, and S.P. Kowalczyk, "High performance SRAMs in 1.5 V, 0.18 μm partially depleted SOI technology," in Dig. of Tech. Papers, Symp. VLSI Circuits, 2002, pp. 74-77.
40. R.V. Joshi, C.T. Chuang, S.K.H. Fung, F. Assaderaghi, M. Sherony, I. Yang, and G. Shahidi, "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM," in Dig. of Tech. Papers, Symp. VLSI Technology, 2001, pp. 75-76.
41. H. Wan, S.K.H. Fung, P. Su, M. Chan, and C. Hu, "Tendency of full depletion due to gate tunneling current," in Proc. IEEE Int. SOI Conf., 2002, pp. 140-141.
42. L. Chang, K.J. Yang, Y.C. Yeo, Y.K. Choi, T.J. King, and C. Hu, "Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs," in Tech. Digest IEDM 2001, pp. 99-102.
43. R.V. Joshi, S.S. Kang, and C.T. Chuang, "3D thermal analysis for SOI and its impact on circuit performance," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices (SISPAD'01), 2001, pp. 242-245.
44. M. Asheghi, B. Behkam, K. Yazdani, R. Joshi, and K.E. Goodson, "Thermal conductivity model for thin silicon-on-insulator layers at high temperatures," in Proc. IEEE Int. SOI Conf., 2002, pp. 51-52.
45. A. Balandin and K.L. Wang, "Significant decrease of the lattice thermal conductivity due to phonon confinement in a free-standing semi-conductor quantum well," Phys. Rev. B., vol. 58, no. 3, pp. 1544-1549, 1998.
46. Y. Tosaka, K. Suzuki, and T Sugii, "α-particle-induced soft errors in submicron SOI SRAM," in Dig. Tech. Papers, Symp. VLSI Technology, 1995, pp. 39-40.
47. L. Wissel, S. Pheasant, R. Loughran, C. LeBlanc, B. Klaasen, "Managing soft errors in ASICs," in Proc. CICC, 2002, pp. 85-88.
48. P. Oldiges, K. Bernstein, D. Heidel, B. Klaasen, E. Cannon, R. Dennard, H. Tang, M. Ieong, and H.-S.P. Wong, "Soft error rate scaling for emerging SOI technology options," in Dig. of Tech. Papers, Symp. VLSI Technology, 2002, pp. 46-47.
49. K. Rim, "Strained Si surface channel MOSFETs for high-performance CMOS technology," in Dig. Tech. Papers, ISSCC 2001, pp. 116-117.
50. K. Rim et al., "Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs," in Dig. of Tech. Papers, Symp. VLSI Technology, 2002, pp. 98-99.
51. S. Takagi, J.L. Hoyt, J.J. Welser, and J.F. Gibbons, "Comparative study of phonon limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 80, pp. 1567-1577, 1996.
52. R. Oberhuber, G. Zandler, and P. Vogl, "Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET's," Phys. Rev. B, vol. 58, p. 9941, 1998.
53. L.J. Huang, J.O. Chu, S. Goma, C.P. D'Emic, S.J. Koester, D.F. Canaperi, P.M. Mooney. S.A. Cordes, J.L. Speidell, R.M. Anderson, and H.-S.P. Wong, "Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding," Dig. of Tech. Papers, Symp. VLSI Technology, 2001, pp. 57-58.
54. K. Kim, C.T. Chuang, K. Rim, and R.V. Joshi, "Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS," Proc. IEEE Int. SOI Conf., 2002, pp. 17-19.
55. K. Kim, R.V. Joshi, and C.T. Chuang, "Strained-Si Devices and Circuit for Low-Power Applications," Proc. Int. Symp. Low Power Electronics and Design, Seoul, Korea, Aug. 25-28, 2003, pp. 180-183.
56. K. Kim, C.T. Chuang, K. Rim, J. Cai, and W.E. Haensch, "Analysis and modeling methodology of Strained-Si channel-on-Insulator (SSOI) MOSFETs," in Proc. Tech. Papers, Int. Symp. VLSI Tech., Syst., Applications, Hsinchu, Taiwan, Oct. 6-8, 2003, pp. 56-59.
57. J. Robertson, and C.W. Chen, "Schottky barrier heights of tantalum oxide, barium strontium titanate, lead zirconate titanate and strontium bismuth tantalite," in Proc. Mat. Res. Soc. Symp., vol. 541, 1999, pp. 443-448.
58. J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vacuum Science & Technology B, vol. 18, no. 3, pp. 1785-1791, May/June 2000.
59. S. Miyazaki, "Photoemission study of energy-band alignments and gap-state density distributions for high-k gate dielectrics," J. Vacuum Sci. Technol. B, vol. 19, no. 6, pp. 2212-2216, Nov./Dec. 2001.
60. R.M. Wallase and G. Wilk, "Alternate gate dielectrics for microelectronics," Mat. Res. Soc. Bulletin, vol. 27, no. 3, pp. 186-191, March 2002.
61. H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara. "Advanced gate dielectric materials for sub-100 nm CMOS," in Tech. Digest IEDM 2002, pp. 625-628.
62. J. McPherson, J. Kim, A. Shanware, H. Mogul, and J. Rodriguez, "Proposed universal relationship between dielectric breakdown and dielectric constant," in Tech. Digest IEDM 2002, pp. 633-636.
63. 2 gate dielectric," in Dig. Tech. Papers, Symp. VLSI Technology, 2002, pp. 12-13.
64. E.J. Nowak, I. Aller, T. Ludwig, K. Kim, R.V. Joshi, C-T. Chuang, K. Bernstein, and R. Puri, "Turning silicon on its edge," IEEE Circuits Devices Mag., vol. 20, no. 1, pp. 20-31, Jan./Feb. 2004.