Maintaining the benefits of CMOS scaling when scaling bogs down

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 169-180

  Nowak, Edward J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; GATES (TRANSISTOR); LITHOGRAPHY; MOSFET DEVICES; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY;

SCALING LIMITATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 0036507826     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0169     Document Type: Review

References (26)

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