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Volumn 20, Issue 1, 2004, Pages 20-31

Turning silicon on its edge

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

EID: 1842865629     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2004.1263404     Document Type: Article
Times cited : (346)

References (24)
  • 3
    • 0032284102 scopus 로고    scopus 로고
    • Device design considerations for double-gate, ground-plane, single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation
    • H-S.P. Wong, D. Frank, and P. Solomon, "Device design considerations for double-gate, ground-plane, single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation," in Tech. Digest IEDM 1998, San Francisco, CA, pp. 407-410.
    • Tech. Digest IEDM 1998, San Francisco, CA , pp. 407-410
    • Wong, H.-S.P.1    Frank, D.2    Solomon, P.3
  • 4
    • 0009544556 scopus 로고    scopus 로고
    • Ultimate MOSFETs on SOI: Ultra thin, single gate, double gate, or ground plane
    • S. Christoloveanu, T. Ernst, D. Munteanu, and T. Ouisse, "Ultimate MOSFETs on SOI: Ultra thin, single gate, double gate, or ground plane," Int. J. High Speed Electron. Syst., vol. 10, no. 1, pp. 217-230, 2000.
    • (2000) Int. J. High Speed Electron. Syst. , vol.10 , Issue.1 , pp. 217-230
    • Christoloveanu, S.1    Ernst, T.2    Munteanu, D.3    Ouisse, T.4
  • 17
    • 0019392817 scopus 로고
    • A new edge-defined approach for submicrometer MOSFET fabrication
    • Jan.
    • W.R. Hunter, T.C. Holloway, P.K. Chatterjee, and A.F. Tasch Jr., "A new edge-defined approach for submicrometer MOSFET fabrication," IEEE Elec. Dev. Let., vol. EDL-2, no. 1, pp. 4-6, Jan. 1981.
    • (1981) IEEE Elec. Dev. Let. , vol.EDL-2 , Issue.1 , pp. 4-6
    • Hunter, W.R.1    Holloway, T.C.2    Chatterjee, P.K.3    Tasch Jr., A.F.4
  • 18
    • 0036494144 scopus 로고    scopus 로고
    • A spacer patterning technology for nanoscale CMOS
    • Mar.
    • Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Elec. Dev., vol. 49, no. 3, pp. 436-441, Mar. 2002.
    • (2002) IEEE Trans. Elec. Dev. , vol.49 , Issue.3 , pp. 436-441
    • Choi, Y.-K.1    King, T.-J.2    Hu, C.3
  • 20
    • 4243442024 scopus 로고    scopus 로고
    • FinGEN, a tool for automated FinFET level generation
    • unpublished
    • V. Gernhöfer, "FinGEN, a tool for automated FinFET level generation," unpublished.
    • Gernhöfer, V.1
  • 21
    • 52949118703 scopus 로고    scopus 로고
    • The double-gate FinFET: Device impact on circuit design
    • (and visual supplements pp. 655-657)
    • I. Aller, "The double-gate FinFET: Device impact on circuit design," in Proc. ISSCC 2003, San Francisco, CA, pp. 14-15 (and visual supplements pp. 655-657).
    • Proc. ISSCC 2003, San Francisco, CA , pp. 14-15
    • Aller, I.1
  • 23
    • 1842864525 scopus 로고    scopus 로고
    • FinFET PowerSPICE compact model
    • unpublished
    • R. Williams and E. Nowak, "FinFET PowerSPICE compact model," unpublished.
    • Williams, R.1    Nowak, E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.