Measurement of history effect in PD/SOI single-ended CPL circuit

IEEE International SOI Conference

Volumn , Issue , 2001, Pages 57-58

  Jenkins, K A ^a   Puri, R ^a   Chuang, C T ^a   Pesavento, F L ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER CIRCUITS; LOGIC CIRCUITS; MOS DEVICES;

COMPLEMENTARY PASS-TRANSISTOR LOGIC (CPL) CIRCUITS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0035167285     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)