Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 4, 2001, Pages 597-604

  Kuang, Jente B ^a,b   Allen, David H ^b   Chuang, Ching Te ^a,c  

^a IEEE   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuit modeling; Circuit sensitivity analysis; CMOS memory circuits; Integrated circuit design; Silicon on insulator technology; SRAM chips

Indexed keywords

CIRCUIT SENSITIVITY ANALYSIS; DYNAMIC BODY CHARGE MODULATION; LATCH TYPE SENSE AMPLIFIER;

CURRENT VOLTAGE CHARACTERISTICS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0035309061     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.913737     Document Type: Article

References (17)

1. SRAM bitline circuits on PD SOI: Advantages and concerns
2. Floating-body effects in partially depleted SOI CMOS circuits
3. SOI for digital CMOS VLSI-design considerations and advances
4. A 7.9/5.5 ps room/low temperature SOI CMOS
5. Analog parameters of short-channel SOI MOSFETs
6. Some do's and dont's for analogue design in SOI CMOS
7. Partially depleted SOI technology for digital logic
8. Scalable PD/SOI CMOS with floating bodies
9. A 0.2 μm 1.8 V SOI 550-MHz 64-b PowerPC microprocessor with copper interconnects
10. A 0.25-μm CMOS SOI technology and its application to 4-Mb SRAM
11. Design issues and insights for low-voltage high-density SOI DRAM
12. A dynamic body discharge technique for SOI circuit applications
13. A new SOI inverter for low-power applications
14. High-speed SOI buffer circuit with the efficient connection of subsidiary MOSFETs for dynamic threshold control
15. A novel dynamic Vt circuit configuration
16. SOI-DRAM circuit technologies for low-power high-speed multigigascale memories
17. Asynchronous sense differential logic