Scaling assessment of fully-depleted SOI technology at the 30 nm gate length generation

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 25-27

  Vandooren, Anne ^a   Jovanovic, D ^a   Egley, S ^a   Sadd, M ^a   Nguyen, B Y ^a   White, B ^a   Orlowski, M ^a   Mogab, J ^a  

^a Digital DNA Laboratories   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MOSFET DEVICES; PERMITTIVITY; QUANTUM THEORY; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; THICKNESS MEASUREMENT; THIN FILMS; THRESHOLD VOLTAGE;

SHORT-CHANNEL EFFECTS (SCE);

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036454454     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044402     Document Type: Conference Paper

References (4)

1. S. Veeraghavan et al., IEEE Trans. Electron Devices, pp. 522-528, 1989.
2. L.T. Su et al., IEEE Electron device letters, vol. 15, no. 5, pp. 183-185, May 1994.
3. M.J. Sherony et al., IEEE Electron Device Letters, vol. 16, no. 3, pp. 100-102, March 1995.
4. T. Ernst et al., Electrochemical society proceedings, vol. 99-3, pp. 329-334.