Managing soft errors in ASICs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 85-88

  Wissel, Larry ^a   Pheasant, Scott ^a   Loughran, Rory ^a   LeBlanc, Chris ^a   Klaasen, Bill ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONICS PACKAGING; EMBEDDED SYSTEMS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; STATIC RANDOM ACCESS STORAGE; TRANSISTORS; VLSI CIRCUITS;

SOFT ERRORS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0036045251     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A new physical mechanism for soft errors in dynamic memories
2. Terrestrial cosmic rays
3. Neutron-Induced boron fission as a major source of soft errors in deep submicron SRAM devices
4. Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview
5. Alpha-SER modeling & simulation for sub- 0.25μm CMOS technology
6. The first copper ASICs: A 12M-Gate technology
7. Accelerated testing for soft-error rate