Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 40-41

  Aller, Ingo ^a   Kroell, Karl Eugen ^a  

^a IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY; SWITCHING CIRCUITS;

GATE DELAY VARIABILITY;

CMOS INTEGRATED CIRCUITS;

EID: 0033324758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)