-
1
-
-
0016116644
-
Design of ion-implanted MOSFET's with very small physical dimensions
-
R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, 1974.
-
(1974)
IEEE J. Solid-State Circuits
, vol.SC-9
, pp. 256-268
-
-
Dennard, R.H.1
Gaensslen, F.H.2
Yu, H.N.3
Rideout, V.L.4
Bassous, E.5
LeBlanc, A.R.6
-
2
-
-
0028459988
-
MOSFET scaling in the next decade and beyond
-
June
-
C. Hu, "MOSFET scaling in the next decade and beyond," Semicond. Int., vol. 17, no. 6, pp. 105-114, June 1994.
-
(1994)
Semicond. Int.
, vol.17
, Issue.6
, pp. 105-114
-
-
Hu, C.1
-
3
-
-
0030403761
-
CMOS technology scaling: 0.1 μm and beyond
-
B. Davari, "CMOS technology scaling: 0.1 μm and beyond," Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, pp. 555-558, 1996.
-
(1996)
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA
, pp. 555-558
-
-
Davari, B.1
-
5
-
-
0001394083
-
Device physics: Pushing the limits
-
P.A. Packan, "Device physics: Pushing the limits," Science, vol. 285, pp. 2079-2081, 1999.
-
(1999)
Science
, vol.285
, pp. 2079-2081
-
-
Packan, P.A.1
-
6
-
-
0033750493
-
Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
-
Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.J. King, J. Bokor, and C. Hu, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Lett., vol. 21, p. 254, 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 254
-
-
Choi, Y.-K.1
Asano, K.2
Lindert, N.3
Subramanian, V.4
King, T.J.5
Bokor, J.6
Hu, C.7
-
7
-
-
0033656171
-
30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D
-
Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.J. King, J. Bokor, and C. Hu, "30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D," in Proc. IEEE 58th Device Research Conf., Denver, CO, 2000, p. 23.
-
Proc. IEEE 58th Device Research Conf., Denver, CO, 2000
, pp. 23
-
-
Choi, Y.-K.1
Jeon, Y.-C.2
Ranade, P.3
Takeuchi, H.4
King, T.J.5
Bokor, J.6
Hu, C.7
-
8
-
-
0034186925
-
Elevated source drain devices using silicon selective epitaxial growth
-
S.B. Samavedam, A. Dip, A.M. Phillips, P.J. Tobin, T. Mihopolous, W.J. Taylor, and O. Adetutu, "Elevated source drain devices using silicon selective epitaxial growth," J. Vac. Sci. Technol. B, vol. 18, pp. 1244-1250, 2000.
-
(2000)
J. Vac. Sci. Technol. B
, vol.18
, pp. 1244-1250
-
-
Samavedam, S.B.1
Dip, A.2
Phillips, A.M.3
Tobin, P.J.4
Mihopolous, T.5
Taylor, W.J.6
Adetutu, O.7
-
9
-
-
0025750677
-
Low-temperature in-situ dry cleaning process for epitaxial layer multiprocessing
-
M. Moslehi, "Low-temperature in-situ dry cleaning process for epitaxial layer multiprocessing," Proc. SPIE-The International Society for Optical Engineering, vol. 1393, pp. 90-108, 1991.
-
(1991)
Proc. SPIE-The International Society for Optical Engineering
, vol.1393
, pp. 90-108
-
-
Moslehi, M.1
-
10
-
-
0034784827
-
Ultra-thin body PMOSFETs with selectively deposited Ge source/drain
-
Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Ultra-thin body PMOSFETs with selectively deposited Ge source/drain," in Proc. Symp. VLSI Technol., Kyoto, Japan, 2001, pp. 19-20.
-
Proc. Symp. VLSI Technol., Kyoto, Japan, 2001
, pp. 19-20
-
-
Choi, Y.-K.1
Ha, D.2
King, T.-J.3
Hu, C.4
-
11
-
-
84886448137
-
Subband structure engineering for performance enhancement of Si MOSFETs
-
S.-I. Takagi, J. Koga, and A. Toriumi, "Subband structure engineering for performance enhancement of Si MOSFETs," Int. Electron Devices Meeting Tech. Dig., Washington, DC, pp. 219-222, 1997.
-
(1997)
Int. Electron Devices Meeting Tech. Dig., Washington, DC
, pp. 219-222
-
-
Takagi, S.-I.1
Koga, J.2
Toriumi, A.3
-
12
-
-
0001114294
-
Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers
-
M. Shoji and S. Horiguchi, "Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers," J. Appl. Phys., vol. 85, pp. 2722-2731, 1999.
-
(1999)
J. Appl. Phys.
, vol.85
, pp. 2722-2731
-
-
Shoji, M.1
Horiguchi, S.2
-
13
-
-
0034872968
-
Threshold voltage shift by quantum confinement in ultra-thin body device
-
Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Threshold voltage shift by quantum confinement in ultra-thin body device," in Proc. IEEE 58th Device Res. Conf., Notre Dame, IN, 2001, pp. 85-86.
-
Proc. IEEE 58th Device Res. Conf., Notre Dame, IN, 2001
, pp. 85-86
-
-
Choi, Y.-K.1
Ha, D.2
King, T.-J.3
Hu, C.4
-
14
-
-
36549104118
-
Bistable conditions for low-temperature silicon expitaxy
-
B. Meyerson, F.J. Himpsel, and K.J. Uram, "Bistable conditions for low-temperature silicon expitaxy," Appl. Phys. Lett., vol. 57, no. 10, p. 1034, 1990.
-
(1990)
Appl. Phys. Lett.
, vol.57
, Issue.10
, pp. 1034
-
-
Meyerson, B.1
Himpsel, F.J.2
Uram, K.J.3
-
15
-
-
0021945007
-
The influence of ion implantation on solid phase epitaxy of amorphous silicon deposited by LPCVD
-
W. Yang-yuan, N.W. Cheung, D.K. Sadana, C. Jou, and M. Strathman, "The influence of ion implantation on solid phase epitaxy of amorphous silicon deposited by LPCVD," Adv. Appl. Ion Implantation, vol. 530, p. 70, 1985.
-
(1985)
Adv. Appl. Ion Implantation
, vol.530
, pp. 70
-
-
Yang-Yuan, W.1
Cheung, N.W.2
Sadana, D.K.3
Jou, C.4
Strathman, M.5
-
16
-
-
0033651358
-
60 nm planarized ultra-thin body solid phase epitaxy MOSFETs
-
P. Xuan, J. Kedzierski, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "60 nm planarized ultra-thin body solid phase epitaxy MOSFETs," 58th Device Res. Conf., Denver, CO, 2000, p. 67.
-
58th Device Res. Conf., Denver, CO, 2000
, pp. 67
-
-
Xuan, P.1
Kedzierski, J.2
Subramanian, V.3
Bokor, J.4
King, T.-J.5
Hu, C.6
-
17
-
-
0026138240
-
1-x PMOS
-
Apr.
-
1-x PMOS," IEEE Electron Device Lett., vol. 12, pp. 154-156, Apr. 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 154-156
-
-
Nayak, D.K.1
Woo, J.C.S.2
Park, J.S.3
Wang, K.4
McWilliams, K.P.5
-
18
-
-
0033901411
-
Nanoscale ultra-thin-body silicon-on-insulator P-MOSFETs with a SiGe/Si heterostructure channel
-
Y-C Yeo, V. Subramanian, J. Kedzierski, P. Xuan, E.H. Anderson, T.-J. King, J. Bokor, and C. Hu, "Nanoscale ultra-thin-body silicon-on-insulator P-MOSFETs with a SiGe/Si heterostructure channel," IEEE Electron Device Lett., vol. 21, p. 161, 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 161
-
-
Yeo, Y.-C.1
Subramanian, V.2
Kedzierski, J.3
Xuan, P.4
Anderson, E.H.5
King, T.-J.6
Bokor, J.7
Hu, C.8
-
19
-
-
0033593712
-
Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors
-
C. Wang, J.P. Snyder, and J.R. Tucker, "Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 74, p. 1174, 1999.
-
(1999)
Appl. Phys. Lett.
, vol.74
, pp. 1174
-
-
Wang, C.1
Snyder, J.P.2
Tucker, J.R.3
-
20
-
-
0034453418
-
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
-
J. Kedzierski, P. Xuan, E.J. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 2000, pp. 57-60.
-
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 2000
, pp. 57-60
-
-
Kedzierski, J.1
Xuan, P.2
Anderson, E.J.3
Bokor, J.4
King, T.-J.5
Hu, C.6
-
21
-
-
0032284102
-
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
-
H.-S.P. Wong, D.J. Frank, and P.M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1998, p. 407.
-
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1998
, pp. 407
-
-
Wong, H.-S.P.1
Frank, D.J.2
Solomon, P.M.3
-
22
-
-
0034453428
-
Gate length scaling and threshold voltage control of double-gate MOSFETs
-
L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 2000, p. 719.
-
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 2000
, pp. 719
-
-
Chang, L.1
Tang, S.2
King, T.-J.3
Bokor, J.4
Hu, C.5
-
23
-
-
0032255808
-
A folded-channel MOSFET for deep-sub-tenth micron era
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron era," Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1998, pp. 1032.
-
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1998
, pp. 1032
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Anderson, E.4
Takeuchi, H.5
Asano, K.6
King, T.-J.7
Bokor, J.8
Hu, C.9
-
24
-
-
0033329310
-
Sub 50-nm FinFET: PMOS
-
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," Int. Electron Devices Meeting Tech. Dig., Washington, DC, 1999, p. 67.
-
Int. Electron Devices Meeting Tech. Dig., Washington, DC, 1999
, pp. 67
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
25
-
-
0034866847
-
Quasi-planar NMOS FinFETs with sub-100 nm gate lengths
-
N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, H. Takeuchi, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Quasi-planar NMOS FinFETs with sub-100 nm gate lengths," 59th Device Res. Conf., Notre Dame, IN, 2001, p. 26.
-
59th Device Res. Conf., Notre Dame, IN, 2001
, pp. 26
-
-
Lindert, N.1
Choi, Y.-K.2
Chang, L.3
Anderson, E.4
Takeuchi, H.5
Lee, W.-C.6
King, T.-J.7
Bokor, J.8
Hu, C.9
-
26
-
-
85056911965
-
Monte Carlo simulation of a 30nm dual-gate MOSFET: How short can Si go?
-
D.J. Frank, S.E. Laux, and M.V. Fischetti, "Monte Carlo simulation of a 30nm dual-gate MOSFET: How short can Si go?" Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1992, pp. 553-556.
-
Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, 1992
, pp. 553-556
-
-
Frank, D.J.1
Laux, S.E.2
Fischetti, M.V.3
-
27
-
-
0012543372
-
-
Avant! Corp. and TMA, Inc.; Fremont, CA
-
Avant! Corp. and TMA, Inc., MEDICI 4.1.0, Fremont, CA.
-
MEDICI 4.1.0
-
-
-
28
-
-
0035060744
-
FinFET: A quasi-planar double-gate MOSFET
-
S.H. tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "FinFET: A quasi-planar double-gate MOSFET," in Proc. Int. Solid State Circuits Conf., San Francisco, CA, 2001, p. 118-119.
-
Proc. Int. Solid State Circuits Conf., San Francisco, CA, 2001
, pp. 118-119
-
-
Tang, S.H.1
Chang, L.2
Lindert, N.3
Choi, Y.-K.4
Lee, W.-C.5
Huang, X.6
Subramanian, V.7
Bokor, J.8
King, T.-J.9
Hu, C.10
-
29
-
-
0034272680
-
Electron transport in a model Si transistor
-
Sept.
-
K. Banoo and M.S. Lundstrom, "Electron transport in a model Si transistor," Solid-State Electron., vol. 44, no. 9, pp. 1689-1695, Sept. 2000.
-
(2000)
Solid-State Electron.
, vol.44
, Issue.9
, pp. 1689-1695
-
-
Banoo, K.1
Lundstrom, M.S.2
-
30
-
-
0031143076
-
Back-gated CMOS on SOIAS for dynamic threshold voltage control
-
May
-
I. Yang, C. Vieri, A. Chandrakasan, and D.A. Antoniadis, "Back-gated CMOS on SOIAS for dynamic threshold voltage control," IEEE Trans. Electron Devices, vol. 44, pp. 822-831, May 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, pp. 822-831
-
-
Yang, I.1
Vieri, C.2
Chandrakasan, A.3
Antoniadis, D.A.4
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