Soft error rate scaling for emerging SOI technology options

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 46-47

  Oldiges, P ^a   Bernstein, K ^a   Heidel, D ^a   Klaasen, B ^a   Cannon, E ^a   Dennard, R ^a   Tang, H ^a   Ieong, M ^a   Wong, H S P ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; ERROR ANALYSIS; GATES (TRANSISTOR);

SOFT ERROR RATE (SER);

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036045605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)