Extreme scaling with ultra-thin Si channel MOSFETs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 267-270

  Doris, Bruce ^a   Ieong, Meikei ^a   Kanarsky, Thomas ^a   Zhang, Ying ^b   Roy, Ronnen A ^b   Dokumaci, Omer ^a   Ren, Zhibin ^a   Jamin, Fen Fen ^a   Shi, Leathen ^b   Natzle, Wesley ^a   Huang, Hsiang Jen ^a   Mezzapelle, Joseph ^a   Mocuta, Anda ^a   Womack, Sherry ^a   Gribelyuk, Michael ^a   Jones, Erin C ^b   Miller, Robert J ^b   Philip Wong, H S ^b   Haensch, Wilfried ^b  

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; OSCILLATORS (ELECTRONIC); OXIDATION; SILICON WAFERS; THRESHOLD VOLTAGE; ULTRATHIN FILMS;

THERMAL OXIDATION;

MOSFET DEVICES;

EID: 0036923554     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. D. Hisamoto, IEDM 2001, p. 429, 2001.
2. M. Ieong et al., SSDM 2002, p. 136, 2002.
3. Y.K. Choi et al., IEEE EDL, vol. 22, p. 447, 2001
4. 2001 ITRS Roadmap.
5. Q. Xiang et al., IEDM 2000, p. 860, 2000.
6. R. Chau et al., IEDM 2000, p. 45, 2000.
7. H. Wakabayashi et al., IEDM 2000, p. 49, 2000.
8. B. Yu et al., VLSI Tech. Symp 2001, p. 9, 2001.
9. B. Yu et al., IEDM 2001, p. 937, 2001.
10. S. Fung et al., IEDM 2001, p. 629, 2001.
11. Z. Ren et. al. Session 2.8, IEDM 2002.