Hysteresis Effect in Pass-Transistor-Based, Partially Depleted SOI CMOS Circuits

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 4, 2000, Pages 625-631

  Puri, Ruchir ^a,b,c,d   Chuang, Ching Te ^a,e,f  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^c INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^d NORTEL NETWORKS   (Canada)

^e NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit modeling; CMOS digital integrated circuits; Silicon on insulator (SOI) technology

Indexed keywords

EID: 0000036097     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.839922     Document Type: Article

References (21)

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