Effects of gate-to-body tunneling current on PD/SOI CMOS latches

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2003-January, Issue , 2003, Pages 291-294

  Chuang, C T ^a   Puri, R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Clocks; Delay; Feedback; Inverters; Latches; Master slave; Partial discharges; Performance analysis; Tunneling; Voltage

Indexed keywords

CLOCKS; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ELECTRON TUNNELING; FEEDBACK; FLIP FLOP CIRCUITS; PARTIAL DISCHARGES;

CMOS LATCHES; DELAY; MASTER SLAVE; MASTER-SLAVE CONFIGURATIONS; PERFORMANCE ANALYSIS; PHYSICAL MECHANISM; QUIESCENT STATE; TUNNELING CURRENT;

SEMICONDUCTOR DEVICES;

EID: 84943248182     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2003.1233694     Document Type: Conference Paper

References (6)

1. W. C. Lee and C. Hu, Dig. Tech. Papers, Symp. VLSI Technology, 2000, pp. 198-199.
2. S. K. H. Fung et. al., Proc. IEEE Int'l SOI Conf., 2000, pp. 122-123.
3. S. K. H. Fung et. al., IEDM Tech. Dig., 2000, pp. 231-234.
4. C. T. Chuang, R. Puri, and K. Bernstein, Extended Abstracts, 2001 International Conf. on Solid State Devices and Materials, Tokyo, Japan, Sept. 26-28, 2001, pp. 262-263.
5. C.T. Chuang and R. Puri, Proc. IEEE Int'l SOI Conf., 2002, pp. 121-122.
6. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design - A System Perspective, Addison-Wesley Publishing Co., 1988.