Advanced gate dielectric materials for sub-100 nm CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 625-628

  Iwai, H ^a   Ohmi, S ^a   Akama, S ^a   Ohshima, C ^a   Kikuchi, A ^a   Kashiwagi, I ^a   Taguchi, J ^a   Yamamoto, H ^a   Tonotani, J ^a   Kim, Y ^a   Ueda, I ^a   Kuriyama, A ^a   Yoshihara, Y ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC PROPERTIES; ELECTRON TUNNELING; GATES (TRANSISTOR); LANTHANUM COMPOUNDS; LEAKAGE CURRENTS; MOLECULAR BEAM EPITAXY; SILICA;

GATE INSULATORS;

DIELECTRIC MATERIALS;

EID: 0036924005     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. B. Yu, H. Wang. A. Joshi, Q. Xiang, E, Ibok. and M.- R. Lin, "15 nm Gate Length Planar CMOS Transistor," IEDM Tech. Dig, Washington D.C., pp.937-939, 2001
2. 3 gate dielectrics with equivalent oxide thickness 5-10 A," Symp. on VLSI Tech, Dig. Tech., Honolulu, HI, pp,16-17, 2000
3. 3 Gate Insulator Film with EOTs of 0.8-1.2 nm," Ext. Abs. SSDM, Tokyo, Japan, pp. 496-497, 2001
4. S. Jeon, K. Im, H. Yang, H. Lee, H. Sim, S Choi, T. Jang, and H. Hwang, "Excellent Electrical Characteristics of Lanthanide (Pr, Nd, Sm, Gd, and Dy) Oxide and Lanthanide-doped Oxide for MOS Gate Dielectric Applications, IEDM Tech, Dig., p. 471-4, 2001
5. E. P. Gusev. D. A. Buchanan, E. Cartier, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okom-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Boajarczuk, L-A. Ragnarsson, P. Ronsheim, K. Rim, R. J. Flemimng, A. Mocuta and A. Ajmera, "Ultrathin high-k gate stacks for advanced CMOS devices," IEDM Tech, Dig., p. 451-454, 2001.
6. Papers in IEDM, Symp VLSI Tech, IWGI, SSDM, EEDERC