Strained-Si devices and circuits for low-power applications

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 180-183

  Kim, Keunwoo ^a   Joshi, R V ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Capacitance; CMOS technology; Energy consumption; Germanium silicon alloys; Integrated circuit technology; MOSFET circuits; Permission; Photonic band gap; Silicon germanium; Threshold voltage

Indexed keywords

BICMOS TECHNOLOGY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DESIGN; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY GAP; ENERGY UTILIZATION; GERMANIUM; GERMANIUM ALLOYS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MOSFET DEVICES; PHOTONIC BAND GAP; POWER ELECTRONICS; SILICON; SILICON ALLOYS; THRESHOLD VOLTAGE;

CMOS TECHNOLOGY; GERMANIUM SILICON ALLOY; INTEGRATED CIRCUIT TECHNOLOGY; MOSFET CIRCUITS; PERMISSION; SILICON GERMANIUM;

LOW POWER ELECTRONICS;

EID: 1542299287     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231858     Document Type: Conference Paper

References (9)

1. K. Kim, et al., "Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS," IEEE Int. SOI conf., Oct. 2002, pp. 17-19.
2. T. Mizuno, et al., "High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate," Symp. on VLSI Tech., June 2002. pp.106-107.
3. K. Rim, et al., "Strained Si NMOSFETs for high performance CMOS technology," Symp. on VLSI Tech., 2001, pp. 59-60.
4. M. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, July 1997, pp. 361-363.
5. K. Kim and J. G. Fossum, "Achieving the ballistic-limit current in Si MOSFETs," Solid-State Electron., vol. 47, April 2003, pp. 721-726.
6. Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, NY: Cambridge University Press, 1998.
7. x MOSFET inversion layer centroid modeling," IEEE Trans. Electron Devices, vol. 48, Oct. 2001, pp. 2447-2449.
8. S. Veeraraghavan and J. G. Fossum, "A Physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD," IEEE Trans. Electron Devices, vol. 35, Nov. 1988, pp. 1866-1875.
9. J. G. Fossum, UFSOI/API-7.0 with UFPDB-2.0, University of Florida, 2002 (http://www.soi.tec.ufl.edu).