DRAM technology perspective for gigabit era

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 598-608

  Kim, Kinam ^a   Hwang, Chang Gyu ^a   Lee, Jong Gil ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; LITHOGRAPHY; METALLIZING; SILICON WAFERS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0032028617     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661221     Document Type: Article

References (51)

1. K. N. Kim, J. Y. Lee, K. H. Lee, B. H. Noh, S. W. Nam, Y. S. Park, Y. H. Kim, H. S. Kim, J. S. Kim, J. K. Park, K. P. Lee, K. Y. Lee, J. T. Moon, J. S. Choi, J. W. Park, and J. G. Lee, "Highly manufacturable 1-Gb SDRAM," in VLSI Tech. Dig. Tech. Papers, June 1997, pp. 9-10, 1997
2. K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, and H. Katto, "A 5-V-only 64-K dynamic RAM," in ISSCC Dig. Tech. Papers, Feb. 1980, pp. 228-229.
3. G. Bronner, H. Aochi, M. Gall, J. Gambino, S. Gernhardt, E. Hammerl, H. Ho, J. Iba, H. Ishiuchi, M. Jaso, R. Kleinhenz, T. Mii, M. Narita, L. Nesbit, W. Neumueller, A. Nitayama, T. Ohiwa, S. Parke, J. Ryan, T. Sato, H. Takato, and S. Yoshikawa, "A fully planarized 0.25-μm CMOS technology for 256-Mbit DRAM and beyond," in VLSI Tech. Dig. Tech. Papers, June 1995, pp. 15-16.
4. 3/Ru stacked capacitors using X-ray lithography," in IEDM Tech. Dig., 1995, pp. 903-906.
5. K. P. Lee, Y. S. Park, D. H. Ko, C. S. Hwang, C. J. Kang, K. Y. Lee, J. S. Kirn, J. K. Park, B. H. Roh, J. Y. Lee, B. C. Kim, J. H. Lee, K. N. Kim, J. W. Park, and J. G. Lee, "A process technology for 1-gigabit DRAM," in IEDM Tech. Dig., 1995, pp. 907-910.
6. S. Takehiro, S. Yamauchi, M. Yoshimaru, and H. Onoda, "The simplest stacked BST capacitor for future DRAM's using a novel lowtemperature growth enhanced crystallization," in VLSI Tech. Dig. Tech. Papers, June 1997, pp. 153-154.
7. H. Hada, T. Tatsumi, K. Miyanaga, S. Iwao, H. Mori, and K. Koyama, "A self-aligned contact technology using anisotropical selective epitaxial silicon for gigabit DRAM's," in IEDM Tech. Dig., 1995, pp. 665-668.
8. H. Koga, N. Kasai, H. Hada, T. Tasumi, H. Mori, S. Iwao, K. Saino, H. Yamaguchi, K. Nakajima, Y. Yamada, K. Tokunaga, S. Hirasawa, K. Yoshida, A. Nishizawa, T. Hashimoto, K. Ando, Y. Kato, K. Takemura, and K. Koyama, "A 0.23-//m2 double self-aligned contact cell for gigabit DRAM's with a Ge-added vertical epitaxal Si pad," in IEDM Tech. Dig., 1996, pp. 589-592.
9. J. K. Park, J. Y. Lee, B. H. Hwang, S. Y. Jo, B. C. Kim, S. K. Jang, S. D. Kwon, D. H. Kim, H. S. Kim, K. N. Kim, J. W. Park, and J. G. Lee, "Isolation merged bit line cell (IMBC) for 1-Gb DRAM and beyond," in IEDM Tech. Dig., 1995, pp. 911-914.
10. J. Y. Lee, K. N. Kim, Y. C. Shin, K. H. Lee, J. S. Kim, D. H. Kim, J. W. Park, and J. G. Lee, "Simultaneously formed storage node contact and metal contact cell (SSMC) for 1-Gb DRAM and beyond," in IEDM Tech. Dig., 1996, pp. 593-596.
11. Y. Kohyama, Y. Ozaki, S. Yoshida, Y. Ishibashi, H. Nitta, S. Inoue, K. Nakamura, T. Aoyama, K. Imai, and N. Hayasaka, "A fully printable, self-aligned and planarized stacked capacitor DRAM cell technology for 1-Gbit DRAM and beyond," in VLSI Tech. Dig. Tech. Papers, June 1997, pp. 17-18.
12. H. S. Kim, D. U. Choi, S. H. Lee, S. K. Lee, J. K. Park, K. N. Kim, and J. W. Park, "Data retention times in SOI-DRAM's," in VLSI Tech. Dig. Tech. Papers, June 1996, pp. 126-127.
13. T. Ohno, M. Takahashi, A. Ohtaka, Y. Sakakibara, and T. Tsuchiya, "Suppression of the parasitic effect in ultra-thin-film n-MOSFETs/SIMOX by Ar ion implantation into source/drain regions," in IEDM Tech. Dig., 1995, pp. 627-630.
14. Y. Hu, C. W. Teng, T. W. Houston, K. Joyner, and T. J. Aton, "Design and performance of SOI pass transistors for 1-Gbit DRAM's," in VLSI Tech. Dig. Tech. Papers, June 1996, pp. 128-129.
15. F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, "Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM," in VLSI Tech. Dig. Tech. Papers, June 1995, pp. 141-142.
16. J. H. Bruning, "Optical lithography-Thirty years and three orders of magnitude: The evolution of optical lithography tools,"Proc. SPIE, vol. 3051, pp. 14-27, 1997.
17. C. J. Willson, "Photoresist materials: Aa historical perspective,"Proc. SPIE, vol. 3051, pp. 28-11, 1997.
18. D. J. Ehrlich, J. Y. Tsao, and C. O. Bozler, "Submicrometer patterning by projected excimer-laser-beam induced chemistry,"J. Vac. Sci. Technol., vol. B3, no. 1, pp. 1-8, 1985.
19. J. R. Caarruthers, "Patterning ULSI circuits,"Proc. SPIE, vol. 2723, pp. 2-14, 1996.
20. P. Paniez and A. Schilitz, "Thermal flow properties of Novolak polymers,"Proc. Microcircuit Eng., vol. 88, pp. 585-589, 1988.
21. J. Shaw, E. Babich, M. Hatzakis, and J. Paraszczak, "Polysiloxanes for optical lithography,"Solid State Technol., pp. 83-89, June 1987.
22. N. Ikegami, A. Yabata, T. Matusui, J. Kanamori, and Y. Horiike, "Characteristics of very high-aspect-ratio contact hole etching,"Jpn. J. Appl. Phys. vol. 36, pt 1, no. 4B, pp. 2470-2476, 1997.
23. W. J. Yoo, J. H. Hahn, H. W. Kim, C. O. Jung, Y. B. Koh, and M. Y. Lee, "Control of etch slope during etching of Pt in Ar/Cl2/O2 plasmas,"Jpn. J. Appl. Phys., vol. 35, pt. 1, no. 4B, pp. 2501-2504, 1996.
24. K. Tokashiki, K. Sato, K. Takemura, S. Yamamichi, P-Y. Lesaicherre, H. Miyamoto, E. Ikawa, and Y. Miyasaka, "Effect of Cl2 addition to U2 plasma on RuU2 etching," in 1994 Dry Process Symp., Dig. Tech. Papers, 1994, pp. 73-78.
25. B. H. Roh, Y. H. Cho, Y. G. Shin, C. K. Hong, S. D. Kwon, K. Y. Lee, H. K. Kang, K. N. Kim, and J. W. Park, "Easily manufacturable shallow trench isolation for gigabit dynamic random access memory,"Jpn. J. Appl. Phys., vol. 35, pp. 4618-4623, 1996.
26. A. Bryant, W. Hansen, and T. Mil, "Characteristics of CMOS device isolation for the ULSI age," in 1EDM Tech. Dig., 1994, pp. 671-674.
27. B. H. Roh, C. S. Yoon, D. U. Choi, M. J. Kim, D. W. Ha, J. Y. Lee, K. N. Kim, and J. W. Park, "Shallow trench isolation for enhancement of data retention times in gigabit DRAM," in SSDM'96 Tech. Dig., pp. 830-832.
28. S. M. Hu, "Defects and device processing: Achievements and limitations," in VLSI Sci. Tech. Electrochem. Soc., 1987, p. 722.
29. T. Hamamoto, S. Sugiura, and S. Sawada, "Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling," in 1EDM Tech. Dig., 1995, pp. 915-918.
30. G. Tae Jeong, K. H. Lee, D.-W. Ha, K. C. Lee, I. G. Kirn, K. H. Kim, and K. Kim, "A high-performance 16 Mb DRAM using gigabit technologies,"IEEE Trans. Electron Devices, vol. 43, pp. 2064-2069, Nov. 1997.
31. B. Davari, C. W. Koburger, R. Schulz, J. D. Warnock, T. Furukawa, M. Jost, Y. Taur, W. G. Schwittek, J. K. DeBrosse, M. L. Kerbaugh, and J. L. Mauer, "A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)," in IEDM Tech. Dig., 1989, pp. 61-64.
32. K. Ishimaru, F. Matsuoka, M. Takahashi, M. Nishigohri, Y. Okayama, Y. Unno, M. Yabuki, K. Umezawa, N. Tsuchiya, O. Fujii, and M. Kinugawa, "Mechanical stress-induced MOSFET punchthrough and process optimization for deep submicron TEOS-O3 filled STI device," in VLSI Tech. Dig. Tech. Papers, June 1997, pp. 123-124.
33. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion implanted MOSFET's with very small physical dimensions,"IEEE J. Solid-State Circuits, vol. SC9, pp. 256-268, Oct. 1974.
34. P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, "The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,"IEEE Electron Device Lett., vol. EDL1, pp. 220-223, 1980.
35. D. Ha, J-h. Sim, and K. Kim, "Cell transistor design using self-aligned local channel implant (SALCI) for 4-Gb DRAM's and beyond," in Tech. Dig. SSDM'97, pp. 514-515.
36. K. W. Kwon, I.-S. Park, D. H. Han, E. S. Kim, S. T. Ahn, and M. Y. Lee, "Ta2O5 capacitors for 1 Gbit DRAM and beyond," in IEDM Tech. Dig., 1994, pp. 835-838.
37. K. W. Kwon, S. O. Park, C. S. Kang, Y. N. Kim, S. T. Ahn, and M. Y. Lee, "Degradation-free Ta2U5 capacitor after BPSG reflow at 850 °C for high-density DRAM's," in IEDM Tech. Dig., 1993, pp. 53-56.
38. M-B. Lee, H-D. Lee, B-L. Park, U-I. Chung, Y-B. Koh, and M-Y. Lee, "Electrical characterization of CVD TIN upper electrode for Ta2Os capacitor," in IEDM Tech. Dig., 1996, pp. 683-686.
39. T. Kaga, Y. Sudoh, H. Goto, K. Shoji, T. Kisu, H. Yamashita, R. Nagai, S. lijima, M. Ohkura, F. Murai, T. Tanaka, Y. Goto, N. Yokoyama, M. Horiguchi, M. Isoda, T. Nishida, and E. Takeda, "A 0.29-//m2 MIMCROWN cell and process technologies for 1-Gbit DRAM's," in IEDM Tech. Dig., 1994, pp. 927-929.
40. 3 thin films on a thick storage node of Ru," in IEDM Tech. Dig., 1995, pp. 115-118.
41. S. Yamamichi, P-Y. Lesaicherre, H. Yamaguchi, T. Takemura, S. Sone, H. Yabuta, K. Sato, T. Tamura, K. Nakajima, S. Ohnishi, K. Tokashiki, Y. Hayashi, Y. Kato, Y. Miyasaka, M. Yoshida, and H. Ono, "An ECR MOCVD (Ba,Sr)TiO3 based stacked capacitor technology with RuO2/Ru/TiN/TiSij; storage nodes for Obit-scale DRAM's," in IEDM Tech. Dig., 1995, pp. 119-122.
42. Y. Shimada, A. Inoue, T. Nasu, Y. Nagano, A. Matsuda, Y. Uemoto, E. Fujii, M. Azuma, Y. Oishi, S. Hayashi, and T. Otsuki, "Temperature-dependent current-voltage characteristics of fully processed Bao.ïSro.aTiOa capacitors integrated in a silicon device,"Jpn. J. Appl. Phys., vol. 35, pp. 140-143, 1996.
43. 3 thin films prepared by RF sputtering for dynamic random access memory application,"Jpn. J. Appl. Phys., vol. 33, pp. 5187-5191, 1994.
44. 3 thin films for ultra-large-scale integrated dynamic random access memory application,"Phys. Lett., vol. 67, pp. 2819-2821, 1995.
45. M. T. Bohr, "Interconnect scaling-The real limiter to high-performance ULSI," in IEDM Tech. Dig., 1995, pp. 241-244.
46. G. Raghavan, C. Chiang, P. B. Anders, S. M. Tzeng, R. Villasol, G. Bai, M. Bohr, and D. B. Fräser, "Diffusion of copper through dielectric films under bias temperature stress,"Thin Solid Films, vol. 262, nos. 1-2, pp. 168-176, 1995.
47. J. Li, T. E. Seidel, and J. W. Mayer, "Copper-based metallization in ULSI structure,"MRS Bulletin, vol. XIX, no. 8, pp. 15-21, 1994.
48. N. Hayasaka, H. Miyajima, Y. Nakasaki and R. Katsumata, "Fluorinedoped SiO2 for low dielectric constant films in sub-half-micron ULSI multilevel interconnection," in SSDM'95 Tech. Dig., pp. 157-159.
49. S. M. Rossnagel, D. Mikalsen, H. Kinoshita, and J. J. Cuomo, "Collimated magnetron sputter deposition,"J. Vac. Sei Technol. A, vol. 9, no. 3, pp. 261-265, 1991.
50. N. Motegi, Y. Kashimoto, K. Nagatani, S. Takahashi, T. Kondo, Y. Mizusawa, and I. Nakayama, "Long-throw low-pressure sputtering technology for very large-scale integrated devices,"J. Vac. Sei Technol. B, vol. 13, no. 4, pp. 1906-1909, 1995.
51. G. A. Dixit, W. Y. Hsu, A. J. Konecni, S. Krishnan, J. D. Luttmer, R. H. Havemann, J. Forster, G. D. Yao, M. Narasimhan, Z. Xu, S. Ramaswami, F. S. Chen, and J. Nulman, "Ion métal plasma (IMP) deposited titanium liners for 0.25/0.18 μm multilevel interconnections," in IEDM Tech. Dig., 1996, pp. 357-360.