A 0.23μm2 Double Self-Aligned Contact Cell for Gigabit DRAMs With a Ge-Added Vertical Epitaxial Si Pald

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 589-592

  Koga, H ^a   Kasai, N ^a   Hada, H ^a   Tatsumi, T ^a   Mori, H ^a   Iwao, S ^a   Saino, K ^a   Yamaguchi, H ^a   Nakajima, K ^a   Yamada, Y ^a   Tokunaga, K ^a   Hirasawa, S ^a   Yoshida, K ^a   Nishizawa, A ^a   Hashimoto, T ^a   Ando, K ^a   Kato, Y ^a   Takemura, K ^a   Koyama, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EPITAXIAL GROWTH; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; ELECTRIC WIRING; GATES (TRANSISTOR); MOSFET DEVICES; RANDOM ACCESS STORAGE; SEMICONDUCTING GERMANIUM; SEMICONDUCTING SILICON; SILICON NITRIDE;

ALIGNMENT TOLERANCE; BIT LINES; BIT-LINE ANDS; CONTACT TECHNOLOGIES; DESIGN RULES; EPITAXIAL SI; ETCH-STOP LAYERS; GERMANIUMS (GE); GIGABIT DRAM; SELF ALIGNED CONTACTS;

DYNAMIC RANDOM ACCESS STORAGE; CELLULAR ARRAYS;

ALIGNMENT TOLERANCE; DOUBLE SELF ALIGNED CONTACT TECHNOLOGY; DYNAMIC RANDOM ACCESS MEMORY; EPITAXIAL PAD; ETCH STOP LAYERS; GROWTH RATE RATIO; STACKED CAPACITOR MEMORY CELL; VERTICAL EPITAXIAL GROWTH;

EID: 18344401973     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554052     Document Type: Conference Paper

References (6)

1. K. P. Lee. et al.,“A Pmcess Tcchnology for 1 Giga-Bit DRAM,” IEDM Tech. Dig.. p.907. (1995).
2. T. Miruno, S. Sawada, Y. Saitoh and S. Shinozaki,“Si,N,/SiO2 Spacer Induced High Reliability in LDDMQSFET and Its Simple Degradation Model,” IEDM Tech. Dig., p.234, (1988).
3. T.Yamada, el al.,“Spread Source/Drain(SSD) MOSFET Using Selective Silicon Growth for 64Mhit DRAMs,” IEEDM Tech. Dig.. p.35, (1989).
4. H. Hada. et al.. “A Self-Aligncd Contact Tcchnology Using Anisotropical Selective Epitaxial Silicon For Giga-Bit DRAMs,” IEDM Tech. Dig., p.665,(1995).
5. Syun-Ming Jang, el al., “Phosphorus doping of Si and Si,.,Ge, at very low pressure,” Appl. Pliys. Lett., Vo1.63, p.1675, (1993).
6. 2/Ru Storage Node on a TiN-capped Plug for 4 Ghil DRAMS and Beyond.” to be presented at 1996 IEDM.