The Impact of Scaling Laws on the Choice of n-Channel or p-Channel for MOS VLSI

IEEE Electron Device Letters

Volumn 1, Issue 10, 1980, Pages 220-223

  Chatterjee, Pallab K ^a   Hunter, W R ^a   Holloway, T C ^a   Lin, Y T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS;

INTEGRATED CIRCUITS;

EID: 0019075967     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1980.25295     Document Type: Article

References (15)

1. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, & A.R. LeBlanc, “Design of Ion-Implanted MOSFETs with very small Physical Dimensions.” IEEE J. Solid St. Circuits, SC-9, p. 256, 1974.
2. L.M. Dong, H. Iwai, Y. Nishi & S. Tagnchi, “P-channel vs N-channel in MOS-ICs of submicron Channel Length.” 11th Conf. on Solid-State Devices, p. 107, Tokyo, 1979.
3. T. Mano, K. Takeya, T. Watanabe, K. Kuichi, T.O. Gana and K. Hirata, “A256K RAM fabricated with Molybdenum-Polysilicon Technology.” ISSCC Tech. Digest p. 234, 1980.
4. R.M. Jecmen, A.A. Ebel, R.J. Smith, V. Kynett, C. Hui, R.D. Pashley, “A25ns4K static RAM.” ISSCC Tech. Digest p. 100, 1979.
5. T.H. Ning, P.W. Cook, R.H. Dennard, C.M. Osburn, S.E. Schuster, H.N. Yu, “1 m MOSFET VLSI Technology: Part IV — Hot Electron Design Constraints.” IEEE Trans. Elect. Dev. ED-26, p. 346, 1978.
6. P.K. Chatterjee, “VLSI Dynamic nMOS Design Constraints due to Drain Induced Primary & Secondary Impactionization.” IEDM Tech. Digest, p. 14, Washington, 1979.
7. S. Kohyma, T. Furuyama, S. Mimura, H. Iizuka, “Non-Thermal Carrier Generating in MOS Structures.” 11th conf. on Solid State Devices, p. 85, Tokyo, 1979.
8. Eric Demoulin, J.A. Greenfield, R.W. Duttun, P.K. Chatterjee, A.F. Tasch, Jr., “Process Statistics of Submicron MOSFETs.” IEDM Tech. Digest p. 34, Washington, 1979.
9. A. Sabnis and J.T. Clemens, “Characterization of the Electron Mobility in the Inverted (100) Si Surface,” IEDM, Tech. p. 18, Washington, 1979.
10. C. Hilsum, “Simple Empirical Relationship Between Mobility & Carrier Concentration.” Electron. Lett, 10, p. 259, (1974).
11. G.W. Taylor, “The Effects of 2-D Charge Sharing on the Above Threshold Characteristics of Short Channel IGFETs.” Solid State Electronics, 1979.
12. P.K. Chatterjee, “Process & Device Modelling.” Final Report, DARPA Contract MDA 0296., 1980.
13. C. Jacobani, C. Canali, G. Ottaviani, A.A. Quaranta, “A Review of Some Charge Transport Properties of Silicon.” Solid State Electronics, 20, p. 77, 1977.
14. H.T. Yuan, S.Y. Chiang, and Y.T. Lin, “Comparison of Interconnection Capacitances on Silicon, Sapphire and Semi-Insulator Gallium Arsenide Substrates.” SISC, New Orleans, 1979.
15. C.A. Lee, R.A. Logan, R.L. Batdorf, J.J. Kleimack, and W. Weigmann, “Ionization Rates of Holes and Electrons in Silicon.” Phys. Rev., 134, A761, 1964.