Fully printable, self-aligned and planarized stacked capacitor DRAM cell technology for 1 Gbit DRAM and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 17-18

  Kohyama, Y ^a   Ozaki, T ^a   Yoshida, S ^a   Ishibashi, Y ^a   Nitta, H ^a   Inoue, S ^a   Nakamura, K ^a   Aoyama, T ^a   Imai, K ^a   Hayasaka, N ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CELLULAR ARRAYS; INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; MASKS; SCANNING ELECTRON MICROSCOPY;

BUILT IN SELF TESTS (BST); DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0030685277     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)