Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1995, Pages 141-142

  Morishita, F ^a   Suma, K ^a   Hirose, M ^a   Tsuruda, T ^a   Yamaguchi, Y ^a   Eimori, T ^a   Oashi, T ^a   Arimoto, K ^a   Inoue, Y ^a   Nishimura, T ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC VARIABLES MEASUREMENT; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; SEMICONDUCTING FILMS; SEMICONDUCTOR JUNCTIONS;

BOOSTED SENSE GROUND SCHEME; DYNAMIC CHARACTERISTICS; DYNAMIC REFRESH ERROR; DYNAMIC RETENTION MODE; LEAKAGE MECHANISM; READ/WRITE OPERATION; STATIC CHARACTERISTICS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0029481651     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)