Mechanical stress induced MOSFET punch-through and process optimization for deep submicron TEOS-O3 filled STI device

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 123-124

  Ishimaru, K ^a   Matsuoka, F ^a   Takahashi, M ^a   Nishigohri, M ^a   Okayama, Y ^a   Unno, Y ^a   Yabuki, M ^a   Umezawa, K ^a   Tsuchiya, N ^a   Fujii, O ^a   Kinugawa, M ^a  

^a Microelectronics Engineering Lab   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CRYSTAL DEFECTS; DIFFUSION IN SOLIDS; IMPURITIES; MOSFET DEVICES; RANDOM ACCESS STORAGE; RESIDUAL STRESSES; SEMICONDUCTOR DEVICE STRUCTURES; STRESS CONCENTRATION;

SHALLOW TRENCH ISOLATION (STI); SOURCE/DRAIN IMPURITY; TETRAETHYLORTHOSILICATE (TEOS);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030679337     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)