A primer on hardware prefetching

Synthesis Lectures on Computer Architecture

Volumn 28, Issue , 2014, Pages 1-69

  Falsafi, Babak ^a   Wenisch, Thomas F ^b  

^a EPFL   (Switzerland)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

address correlated prefetching; branch directed prefetching; discontinuity prefetching; execution based prefetching; global history buffer; hardware prefetching; Markov prefetcher; next line prefetching; spatial memory streaming; stride prefetching; temporal memory streaming

Indexed keywords

COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; HARDWARE; MICROPROCESSOR CHIPS; WALLS (STRUCTURAL PARTITIONS); MEMORY ARCHITECTURE; RECONFIGURABLE HARDWARE;

GLOBAL HISTORY BUFFER; MARKOV PREFETCHER; PREFETCHING; SPATIAL MEMORY; STRIDE PREFETCHING; TEMPORAL MEMORY;

CACHE MEMORY;

EID: 84902193542     PISSN: 19353235     EISSN: 19353243     Source Type: Book Series    
DOI: 10.2200/S00581ED1V01Y201405CAC028     Document Type: Article

References (131)

1. W. A. Wulf and S. A. McKee. "Hitting the Memory Wall: Implications of the Obvious." ACM SIGARCH Computer Architecture News, v. 23 no. 1, 1995. DOI: 10.1145/216585.216588. xiii
2. D. Lustig, A. Bhattacharjee, and M. Martonosi. "TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs." ACM Transactions on Architecture and Code Optimization, v. 10, no. 1, 2013. DOI: 10.1145/2445572.2445574. xiii
3. J. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach, 4th ed. DOI: 10.1.1.115.1881. 1
4. B. Jacob. "Te Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It." Synthesis Lectures on Computer Architecture, v. 4, no. 1, 2009. DOI: 10.2200/S00201ED1V01Y200907CAC007. 2
5. A. J. Smith. "Sequential Program Prefetching in Memory Hierarchies." Computer, v. 11, no. 12, 1978. DOI: 10.1109/C-M.1978.218016. 7, 15
6. D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo. "Te IBM System/360 Model 91: Machine Philosophy and Instruction-Handling." IBM Journal of Research and Development, v. 11 no. 1, 1967. DOI: 10.1147/rd.111.0008. 8
7. M. Ferdman, T F Wenisch, A. Ailamaki, B. Falsaf, A. Moshovos. "Temporal Instruction Fetch Streaming." In Proc. of the 41st Annual ACM/IEEE International Symposium on Microarchitecture, 2008. DOI: 10.1109/MICRO.2008.4771774. 8, 10, 12
8. P. Ranganathan, K. Gharachorloo, S. V. Adve, and L. A. Barroso. "Performance of Data-base Workloads on Shared-Memory Systems With Out-Of-Order Processors." In Proc. of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998. DOI: 10.1145/291069.291067. 8
9. A. Ramirez, O. J. Santana, J. L. Larriba-Pey and M. Valero. "Fetching Instruction Streams." In Proc. of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, 2002. 8
10. O. J. Santana, A. Ramirez, and M. Valero. "Enlarging Instruction Streams." IEEE Trans-actions on Computers, v. 56, no. 10, 2007. DOI: 10.1109/TC.2007.70742. 8, 11
11. I-C. K. Chen, C-C. Lee, and T. N. Mudge. "Instruction Prefetching Using Branch Pre-diction Information." In Proc. of the IEEE International Conference on Computer Design, 1997. DOI: 10.1109/ICCD.1997.628926. 9
12. G. Reinman, B. Calder, and T. Austin. "Fetch Directed Instruction Prefetching." In Proc. of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999. 9
13. A. V. Veidenbaum, Q. Zhao, and A. Shameer. "Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors." International Journal of High Speed Computing, v. 10, no. 1, 1999. DOI: 10.1142/ S0129053399000065. 9
14. R. Panda, P. V. Gratz, and D. A. Jiménez. "B-Fetch: Branch Prediction Directed Prefetch-ing for In-Order Processors." In Proc. of the 18th International Symposium on High-Performance Computer Architecture, 2012. DOI: 10.1109/L-CA.2011.33. 9
15. T. Sherwood, S. Sair, and B. Calder. "Predictor-Directed Stream Bufers." In Proc. of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, 2000. DOI: 10.1145/360128.360135. 9
16. J. Pierce, and T. N. Mudge. "Wrong-Path Instruction Prefetching." In Proc. of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, 1996. 11
17. V. Srinivasan, E. S. Davidson, G. S. Tyson, M. J. Charney, and T. R. Puzak. "Branch History Guided Instruction Prefetching." In Proc. of the 7th International Symposium on High-Performance Computer Architecture, 2001. DOI: 10.1109/HPCA.2001.903271. 11
18. Y. Zhang, S. Haga, and R. Barua. "Execution History Guided Instruction Prefetch-ing." In Proc. of the 16th Annual International Conference on Supercomputing, 2002. DOI: 10.1145/514191.514220. 11
19. Q. Jacobson, E. Rotenberg, and J. E. Smith. "Path-Based Next Trace Prediction." In Proc. of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, 1997. DOI: 10.1109/MICRO.1997.645793. 11
20. M. Annavaram, J. M. Patel, and E. S. Davidson. "Call Graph Prefetching for Data-base Applications." ACM Transactions on Computer Systems, v. 21, no. 4, 2003. DOI: 10.1145/945506.945509. 11
21. L. Spracklen, Y. Chou, and S. G. Abraham. "Efective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications." In Proc. of the 11th International Symposium on High-Performance Computer Architecture, 2005. DOI: 10.1109/HPCA.2005.13. 11
22. T. M. Aamodt, P. Chow, P. Hammarlund, H. Wang, and J. P. Shen. "Hardware Support for Prescient Instruction Prefetch." Proc. of the 10th International Symposium on High-Per-formance Computer Architecture, 2004. DOI: 10.1109/HPCA.2004.10028.12
23. C-K. Luk, T. C. Mowry. "Cooperative Prefetching: Compiler and Hardware Support for Efective Instruction Prefetching In Modern Processors." In Proc. of the 31st annual ACM/IEEE International Symposium on Microarchitecture, 1998. DOI: 10.1109/MICRO.1998.742780.12
24. K. Sundaramoorthy, Z. Purser, and E. Rotenberg. "Slipstream Processors: Improving Both Performance and Fault Tolerance." In Proc. of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000. DOI: 10.1145/356989.357013. 12
25. C. Zilles and G. Sohi. "Execution-Based Prediction Using Speculative Slices." In Proc. of the 28th Annual International Symposium on Computer Architecture, 2001. DOI: 10.1145/379240.379246. 12
26. A. Kolli, A. Saidi, and T. F. Wenisch. "RDIP: Return-Address-Stack Directed Instruction Prefetching." In Proc. of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013. DOI: 10.1145/2540708. 2540731. 13
27. M. Ferdman, C. Kaynak, and B. Falsaf. "Proactive Instruction Fetch." In Proc. of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011. DOI: 10.1145/2155620.2155638. 14
28. C. Kaynak, B. Grot, and B. Falsaf. "Shift: Shared History Instruction Fetch for Lean-Core Server Processors." In Proc. of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013. DOI: 10.1145/2540708.2540732. 14
29. J.-L. Baer and T.-F Chen. "An Efective On-Chip Preloading Scheme to Reduce Data Access Penalty." In Proc. of Supercomputing, 1991. DOI: 10.1145/125826.125932. 15, 16
30. F Dahlgren and P. Stenstrom. "Efectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors." In Proc. of the 1st IEEE Symposium on High-Performance Computer Architecture, 1995. DOI: 10.1109/HPCA.1995.386554. 16
31. Y. Ishii, M. Inaba and K. Hiraki. "Access Map Pattern Matching for High Performance Data Cache Prefetch." Journal of Instruction-Level Parallelism, v. 13, 2011. 16, 28
32. S. Sair, T. Sherwood, and B. Calder. "A Decoupled Predictor-Directed Stream Prefetch-ing Architecture." IEEE Transactions on Computers, v. 52, no. 3, 2003. DOI: 10.1109/TC.2003.1183943. 16
33. I. Hur and C. Lin. "Memory Prefetching Using Adaptive Stream Detection." In Proc. of the 39th Annual ACM/IEEE International Symposium on Microarchitecture, 2006. DOI: 10.1109/MICRO.2006.32. 16, 35
34. N. P. Jouppi. "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Bufers." In Proc. of the 17th Annual International Symposium on Computer Architecture, 1990. DOI: 10.1145/325164.325162. 16, 24
35. S. Palacharla and R. E. Kessler. "Evaluating Stream Bufers As a Secondary Cache Place-ment." In Proc. of the 21st Annual International Symposium on Computer Architecture, 1994. 17
36. C. Zhang and S. A. McKee. "Hardware-Only Stream Prefetching and Dynamic Access Ordering." In Proc. of the 14th Annual International Conference on Supercomputing, 2000. DOI: 10.1145/335231.335247. 17
37. S. Iacobovici, L. Spracklen, S. Kadambi, Y. Chou and S. G. Abraham. "Efective Stream-Based and Execution-Based Data Prefetching." In Proc. of the 18th Annual International Conference on Supercomputing, 2004. DOI: 10.1145/1006209.1006211. 17
38. J-L. Baer, J-L., and G. R. Sager. "Dynamic Improvement of Locality in Virtual Mem-ory Systems." IEEE Transactions on Software Engineering, v. 1, 1976. DOI: 10.1109/TSE.1976.233801. 17
39. M. J. Charney and A. P. Reeves. "Generalized Correlation-Based Hardware Prefetching." Technical Report EE-CEG-95-1, School of Electrical Engineering, Cornell University, Feb. 1995. 17
40. M. J. Charney. Correlation-Based Hardware Prefetching, 1996. Ph.D. diss., Cornell Uni-versity, 1996. 17
41. T. M. Chilimbi and M. Hirzel. "Dynamic Hot Data Stream Prefetching for Gener-al-Purpose Programs." In Proc. of the Conference on Programming Language Design and Implementation, 2002. DOI: 10.1145/512529.512554. 17, 19, 20, 24, 36
42. T. F Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsaf. "Temporal Streaming of Shared Memory." In Proc. of the 32nd Annual International Symposium on Computer Architecture, June 2005. DOI: 10.1109/ISCA.2005.50. 17, 20, 22
43. C.-K. Luk and T. C. Mowry "Compiler Based Prefetching for Recursive Data Struc-tures." In Proc. of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, 1996. DOI: 10.1145/237090.237190. 17, 36
44. A. Roth, A. Moshovos, and G. S. Sohi. "Dependence Based Prefetching for Linked Data Structures." In Proc. of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998. DOI: 10.1145/291069.291034.17, 33
45. A. Roth and G. S. Sohi. "Efective Jump Pointer Prefetching for Linked Data Structures." In Proc. of the 26th Annual International Symposium on Computer Architecture, 1999. DOI: 10.1109/ISCA.1999.765944. 17, 33
46. J. Collins, S. Sair, B. Calder, and D. M. Tullsen. "Pointer Cache Assisted Prefetching." In Proc. of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, 2002. DOI: 10.1109/MICRO.2002.1176239. 17
47. R. Cooksey, S. Jourdan, and D. Grunwald. "A Stateless, Content-Directed Data Prefetch-ing Mechanism." In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002. DOI: 10.1145/605397.605427. 18
48. E. Ebrahimi, O. Mutlu, and Y. N. Patt. "Techniques for Bandwidth-Efcient Prefetching of Linked Data Structures in Hybrid Prefetching Systems." In Proc. of the 15th International Symposium on High Performance Computer Architecture, 2009. DOI: 10.1109/HPCA.2009.4798232. 18
49. D. Joseph and D. Grunwald. "Prefetching Using Markov Predictors." In Proc. of the 24th Annual International Symposium on Computer Architecture, 1997. DOI: 10.1145/264107.264207. 18, 19
50. D. Joseph and D. Grunwald. "Prefetching Using Markov Predictors." IEEE Transactions on Computers, v. 48 no. 2, 1999. DOI: 10.1109/12.752653. 18
51. A.-C. Lai, C. Fide, and B. Falsaf. "Dead-Block Prediction and Dead-Block Correlating Prefetchers." In Proc. of the 28th Annual International Symposium on Computer Architecture, 2001. DOI: 10.1145/379240.379259. 19, 20, 21
52. Y. Solihin, J. Lee, and J. Torrellas. "Using a User-Level Memory Tread for Correlation Prefetching." In Proc. of the 29th Annual International Symposium on Computer Architecture, May 2002. DOI: 10.1109/ISCA.2002.1003576. 20, 22
53. Y. Solihin, J. Lee, and J. Torrellas. "Correlation Prefetching with a User-Level Memory Tread." IEEE Transactions on Parallel and Distributed Systems, v. 14, no. 6, 2003. DOI: 10.1109/TPDS.2003.1206504. 20
54. M. Ferdman and B. Falsaf. "Last-Touch Correlated Data Streaming." In IEEE Interna-tional Symposium on Performance Analysis of Systems and Software, 2007. DOI: 10.1109/ISPASS.2007.363741. 20, 21, 22
55. T.F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsaf, and A. Moshovos. "Temporal Streams in Commercial Server Applications." In Proc. of the IEEE International Symposium on Workload Characterization, 2008. DOI: 10.1109/IISWC.2008.4636095. 20, 22, 32
56. Y. Chou, B. Fahs, and S. Abraham. "Microarchitecture Optimizations for Exploiting Memory-Level Parallelism." In Proc. of the 31st Annual International Symposium on Computer Architecture, 2004. DOI: 10.1145/1028176.1006708. 20
57. Y. Chou. "Low-Cost Epoch-Based Correlation Prefetching for Commercial Applica-tions." In Proc. of the 40th Annual ACM/IEEE International Symposium on Microarchitecture, 2007. DOI: 10.1109/MICRO.2007.39. 20
58. N. Kohout, S. Choi, D. Kim, and D. Yeung. "Multi-Chain Prefetching: Efective Ex-ploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes." In Proc. of the International Conference on Parallel Architectures and Compilation Techniques, 2001. DOI: 10.1109/PACT.2001.953307. 24
59. P. Díaz and M. Cintra. "Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching." In Proc. of the 36th Annual International Symposium on Computer Architecture, 2009. DOI: 10.1145/1555754.1555767. 24
60. A-C. Lai, and B. Falsaf. "Selective, Accurate, and Timely Self-Invalidation Using Last-Touch Prediction." In Proc. of the 27th Annual International Symposium on Computer Architecture, 2000. DOI: 10.1145/339647.339669. 20, 28
61. Z. Hu, S. Kaxiras, and M. Martonosi. "Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior." In Proc. of the 29th Annual International Symposium on Computer Architecture, 2002. DOI: 10.1109/ISCA.2002.1003579. 20, 21
62. H. Liu, M. Ferdman, J. Huh, and D. Burger. "Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efciency." In Proc. of the 41st Annual ACM/IEEE International Symposium on Microarchitecture, 2008. DOI: 10.1109/MICRO.2008.4771793. 20, 21
63. T. R. Puzak. Analysis of Cache Replacement-Algorithms, 1985. Ph.D. diss., Univ. Massachu-setts, Amherst, 1985. 20
64. A. Mendelson, D. Tiebaut, and D. K. Pradhan. "Modeling Live and Dead Lines in Cache Memory Systems." IEEE Transactions on Computers, v. 4 2, n o. 1. DOI: 10.1109/12.192209. 20
65. D. A. Wood, M. D. Hill, and R. E. Kessler. "A Model for Estimating Trace-Sample Miss Ratios." In Proc. of the 1991 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 1991. DOI: 10.1145/107971. 107981. 20
66. Z. Hu, M. Martonosi, and S. Kaxiras. "TCP: Tag Correlating Prefetchers." In Proc. of the 9th IEEE Symposium on High-Performance Computer Architecture, 2003. DOI: 10.1109/HPCA.2003.1183549. 21
67. T. F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsaf, A. Moshovos. "Practical Of-Chip Meta-Data for Temporal Memory Streaming." In Proc. of the 15th International Symposium on High Performance Computer Architecture, 2009. DOI: 10.1109/HPCA.2009.4798239. 22, 25
68. K. J. Nesbit and J. E. Smith. "Data Cache Prefetching Using a Global History Bufer." In Proc. of the 10th IEEE Symposium on High-Performance Computer Architecture, 2004. DOI: 10.1109/HPCA.2004.10030. 22, 23, 24, 26, 27, 28
69. K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith. "AC/DC: An Adaptive Data Cache Prefetcher." In Proc. of the 13th International Conference on Parallel Architectures and Compilation Techniques, 2004. DOI: 10.1109/PACT.2004.1342548. 23, 24, 27
70. T. F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsaf and A. Moshovos. "Making Ad-dress-Correlated Prefetching Practical." IEEE Micro, v. 30, no. 1, 2010. DOI: 10.1109/MM.2010.21. 25
71. I. Chung, C. Kim, H.-F. Wen, and G. Cong. "Application Data Prefetching on the IBM Blue Gene/Q Supercomputer." In International Conference on High Performance Computing, Networking, Storage and Analysis, 2012. DOI: 10.1109/SC.2012.19. 25
72. A. Jain and C. Lin. "Linearizing Irregular Memory Accesses for Improved Correlated Prefetching." In Proc. of the 46th Annual ACM/IEEE International Symposium on Microarchitecture, 2013. DOI: 10.1145/2540708. 2540730. 22, 25
73. G. B. Kandiraju and A. Sivasubramaniam. "Going the Distance for Tlb Prefetching: An Application-Driven Study." In Proc. of the 29th Annual International Symposium on Computer Architecture, 2002. DOI: 10.1109/ISCA.2002.1003578. 27
74. M. Grannaes, M. Jahre, and L. Natvig. "Storage Efcient Hardware Prefetching Using Delta Correlating Prediction Tables." Journal of Instruction-Level Parallelism, v. 13, 2011. 28
75. M. Dimitrov and H. Zhou. "Combining Local and Global History for High Perfor-mance Data Prefetching." Journal of Instruction-Level Parallelism, v. 13, 2011. 28
76. G. Liu, Z. Huang, J-K. Peir, X. Shi, and L. Peng. "Enhancements for Accurate and Timely Streaming Prefetcher." Journal of Instruction-Level Parallelism, v. 13, 2011. 28
77. L. M. Ramos, J. L. Briz, P. E. Ibáñez, and V. Viñals. "Multi-Level Adaptive Prefetching Based on Performance Gradient Tracking." Journal of Instruction-Level Parallelism, v. 13, 2011. 28
78. A. Sharif and H-H. Lee. "Data Prefetching by Exploiting Global and Local Access Pat-terns. " Journal of Instruction-Level Parallelism, v. 13, 2011. 28
79. S. S. Mukherjee and M. D. Hill. "Using Prediction to Accelerate Coherence Protocols." In Proc. of the 25th Annual International Symposium on Computer Architecture, 1998. DOI: 10.1109/ISCA.1998.694773. 28
80. S. Kaxiras, J. R. Goodman. "Improving CC-NUMA Performance Using Instruc-tion-Based Prediction." In Proc. of the 5th International Symposium on High-Performance Computer Architecture, 1999. DOI: 10.1109/HPCA.1999.744359. 28
81. S. Kumar and C. Wilkerson. "Exploiting Spatial Locality in Data Caches Using Spatial Footprints." In Proc. of the 25th Annual International Symposium on Computer Architecture, 1998. DOI: 10.1145/279358.279404. 28, 30
82. S. Somogyi, T. F. Wenisch, A. Ailamaki, B. Falsaf, and A. Moshovos. "Spatial Memory Streaming." In Proc. of the 33rd Annual International Symposium on Computer Architecture, 2006. DOI: 10.1109/ISCA.2006.38. 29, 31, 32
83. C. F Chen, S.-H. Yang, B. Falsaf, and A. Moshovos. "Accurate and Complexity-Efective Spatial Pattern Prediction." In Proc. of the 10th IEEE Symposium on High-Performance Computer Architecture, Feb. 2004. DOI: 10.1109/HPCA.2004.10010. 29, 30
84. M. Ferdman, S. Somogyi, and B. Falsaf. "Spatial Memory Streaming with Rotated Pat-terns." 1st JILP Data Prefetching Championship, 2009. 29
85. S. Somogyi, T. F Wenisch, M. Ferdman, and B. Falsaf. "Spatial Memory Streaming." Journal of Instruction-Level Parallelism, v. 13, 2011. DOI: 10.1109/ISCA.2006.38. 29
86. A. Seznec. "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio." In Proc. of the 21st Annual International Symposium on Computer Architecture, 1994. DOI: 10.1145/191995.192072. 30
87. M. D. Powell, S-H. Yang, B. Falsaf, K. Roy, and T N. Vijaykumar. "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories." In Proc. of the International Symposium on Low Power Electronics and Design, 2000. DOI: 10.1145/344166.344526. 30
88. J. F Cantin, M. H. Lipasti, and J. E. Smith. "Stealth Prefetching." In Proc. of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006. DOI: 10.1145/1168857.1168892. 31
89. I. Burcea, S. Somogyi, A. Moshovos, and B. Falsaf. "Predictor Virtualization." In Proc. of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008. DOI: 10.1145/1346281.1346301. 32
90. T. F. Wenisch. Temporal memory streaming. Ph.D. diss., Carnegie Mellon University, 2007. 32
91. S. Somogyi, T. F. Wenisch, A. Ailamaki, and B. Falsafi. "Spatio-Temporal Memory Streaming." In Proc. of the 36th Annual International Symposium on Computer Architecture, 2009. DOI: 10.1145/1555754.1555766. 32, 33
92. M. Annavaram, J. M. Patel, and E. S. Davidson. "Data Prefetching by Dependence Graph Precomputation." In Proc. of the 28th Annual International Symposium on Computer Architecture, 2001. DOI: 10.1109/ISCA.2001.937432. 33
93. J. D. Collins, H. Wang, D. M. Tullsen, C. Hughes, Y.-F Lee, D. Lavery, and J. P. Shen. "Speculative Precomputation: Long-Range Prefetching of Delinquent Loads." In Proc. of the 28th Annual International Symposium on Computer Architecture, 2001. DOI: 10.1145/379240.379248. 33
94. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen. "Dynamic Speculative Precompu-tation." In Proc. of the 34th Annual ACM/IEEE International Symposium on Microarchitecture, 2001. 33
95. I. Ganusov and M. Burtscher. "Future execution: A Hardware Prefetching Technique for Chip Multiprocessors." In Proc. of the 14th International Conference on Parallel Architectures and Compilation Techniques, 2005. DOI: 10.1109/PACT.2005.23. 33
96. I. Ganusov and M. Burtscher. "Future Execution: A Prefetching Mechanism that Uses Multiple Cores to Speed Up Single Treads." ACM Transactions on Architecture and Code Optimization, v. 3, no. 4, 2006. DOI: 10.1145/1187976.1187979. 33
97. J. Lee, C. Jung, D. Lim, and Y. Solihin. "Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems." IEEE Transactions on Parallel and Distributed Systems, v. 20, no. 9, 2009. DOI: 10.1109/TPDS.2008. 224. 33
98. W Zhang, D. M. Tullsen, and B. Calder. "Accelerating and Adapting Precomputation Treads for Efcient Prefetching." In Proc. of the 13th International Symposium on High Performance Computer Architecture, 2007. DOI: 10.1109/HPCA.2007.346187. 33
99. R. S. Chappell, F Tseng, A. Yoaz, and Y. N. Patt. " Microarchitectural Support for Pre-computation Microthreads." In Proc. of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, 2002. DOI: 10.1109/MICRO.2002.1176240. 33
100. M. Kamruzzaman, S. Swanson, and D. M. Tullsen. "Inter-Core Prefetching for Multicore Processors Using Migrating Helper Treads." In Proc. of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011. DOI: 10.1145/1950365.1950411. 33
101. A. Roth and G. S. Sohi. "Speculative Data-Driven Multithreading." In Proc. of the 7th International Symposium on High-Performance Computer Architecture, 2001. DOI: 10.1109/HPCA.2001.903250. 33
102. J. Dundas and T. N. Mudge. "Improving Data Cache Performance by Pre-Executing Instructions under a Cache Miss." In Proc. of the 11th Annual International Conference on Supercomputing, 1997. DOI: 10.1145/263580.263597. 34
103. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-Of-Order Processors." In Proc. of the 9th International Symposium on High-Performance Computer Architecture, 2003. DOI: 10.1109/HPCA2003.1183532. 34
104. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. "Runahead execution: An Efective Alternative to Large Instruction Windows." IEEE Micro, v. 23, no. 6, 2003. DOI: 10.1109/MM.2003.1261383.34
105. O. Mutlu, H. Kim, and Y. N. Patt. "Techniques for Efficient Processing in Runahead Execution Engines." In Proc. of the 32nd Annual International Symposium on Computer Architecture, 2005. DOI: 10.1109/ISCA.2005.49. 34
106. O. Mutlu, H. Kim, and Y N. Patt. "Efficient Runahead Execution: Power-Efcient Memory Latency Tolerance." IEEE Micro, v. 26, no. 1, 2006. DOI: 10.1109/MM.2006.10. 34
107. S. T Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton. "Continual Flow Pipelines." In Proc. of the International Conference on Architectural Support for Programming Languages and Operating Systems, 2004. DOI: 10.1145/1024393.1024407. 34
108. A. Hilton, S. Nagarakatte, and A. Roth. "iCFP: Tolerating All-Level Cache Misses in In-Order Processors." In Proc. of the 15th International Symposium on High Performance Computer Architecture, 2009. DOI: 10.1109/MM.2010.20. 34
109. H. Cui and S. Suleyman. "Extending Data Prefetching to Cope with Context Switch Misses." In Proc. of the International Conference on Computer Design, 2009. DOI: 10.1109/ICCD.2009.5413144. 34, 35
110. D. Daly and H. W Cain. "Cache Restoration for Highly Partitioned Virtualized Systems." In Proc. of the 18th Annual International Symposium on High Performance Computer Architecture, 2012. DOI: 10.1109/HPCA.2012.6169029. 34
111. J. Zebchuk, H. W. Cain, X. Tong, V. Srinivasan and A. Moshovos. "RECAP: A Region-Based Cure for the Common Cold (Cache)." In Proc. of the 19th Annual International Symposium on High Performance Computer Architecture, 2013. DOI: 10.1145/2370816.2370887. 34
112. K. Chakraborty, P. M. Wells, and G. S. Sohi. "Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-Te-Fly" In Proc. of the 12th International conference on Architectural Support for Programming Languages and Operating Systems, 2006. DOI: 10.1145/1168857.1168893. 35
113. I. Atta, P. Tozun, A. Ailamaki, and A. Moshovos. "SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads." In Proc. of the 2012 45th Annual ACM/IEEE International Symposium on Microarchitecture, 2012. DOI: 10.1109/MICRO.2012.26. 35
114. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt. "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efciency of Hardware Prefetchers." In Proc. of the 13th International Symposium on High Performance Computer Architecture, 2007. DOI: 10.1109/HPCA.2007.346185.
115. E. Ebrahimi, O. Mutlu, C. J. Lee, Y. N. Patt. "Coordinated Control of Multiple Prefetches in Multi-Core Systems." In Proc. of the 42nd Annual ACM/IEEE International Symposium on Microarchitecture, 2009. DOI: 10.1145/1669112.1669154. 35
116. C. J. Lee, V. Narasiman, O. Mutlu, Y. N. Patt, "Improving Memory Bank-Level Parallelism in the Presence of Prefetching." In Proc. of the 42nd Annual ACM/IEEE International Symposium on Microarchitecture, 2009. DOI: 10.1145/1669112.1669155. 35
117. W.-f Lin, S. Reinhardt, and D. Burger. "Reducing DRAM Latencies with an Integrated Memory Hierarchy Design." In Proc. of the 7th International Symposium on High Performance Computer Architecture, 2001. DOI: 10.1109/HPCA.2001.903272. 35
118. C-J. Wu, A. Jaleel, M. Martonosi, S. Steely Jr, and J. Emer. "PACMan: Prefetch-Aware Cache Management for High Performance Caching." In Proc. of the 44th Annual ACM/IEEE International Symposium on Microarchitecture, 2011. DOI: 10.1145/2155620.2155672. 35
119. S. Verma, D. M. Koppelman, and L. Peng. "Efcient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness." Journal of Instruction-Level Parallelism, v. 13, 2011. 35
120. S. Chen, A. Ailamaki, P. B. Gibbons, and T. C. Mowry "Improving Hash Join Performance through Prefetching." In Proc. of the 20th International Conference on Data Engineering, 2004. DOI: 10.1109/ICDE.2004.1319989. 36
121. S. Chen, P. B. Gibbons, and T. C. Mowry. "Improving Index Performance through Prefetching." In Proc. of the 20th Annual ACM International Conference on Management of Data, 2001. DOI: 10.1145/375663. 375688. 36
122. T. C. Mowry, M. S. Lam, and A. Gupta. "Design and Evaluation of a Compiler Algorithm for Prefetching." In Proc. of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, 1992. DOI: 10.1145/143365.143488.36
123. Z. Wang, D. Burger, K. S. McKinley, S. K. Reinhardt, and C. C. Weems. "Guided Region Prefetching: A Cooperative Hardware/Software Approach." In Proc. of the 30th Annual International Symposium on ComputerArchitecture, 2003.DOI: 10.1145/859618.859663. 36
124. D. Koufaty, X. Chen, D. Poulsen, and J. Torrellas. "Data Forwarding in Scalable Shared-Memory Multiprocessors." In Proc. of the 9th Annual International Conference on Supercomputing, 1995. DOI: 10.1145/224538.224569. 36
125. C.-K. Luk and T. C. Mowry. "Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation." In Proc. of the 26th Annual International Symposium on Computer Architecture, 1999. DOI: 10.1145/300979.300987. 36
126. J. H. Ahn, W. J. Dally, B. Khailany, U. J. Kapasi, and A. Das. "Evaluating the Imagine Stream Architecture." In Proc. of the 31st Annual International Symposium on Computer Architecture, 2004. 36
127. W. J. Dally, F Labonte, A. Das, P. Hanrahan, J.-H. Ahn, J. Gummaraju, M. Erez, N. Jayasena, I. Buck, T. J. Knight, and U. J. Kapasi. "Merrimac: Supercomputing with Streams." In Proc. of 'Supercomputing, 2003. DOI: 10.1145/1048935.1050187. 36
128. M. I. Gordon, W. Thies, M. Karczmarek, J. Lin, A. S. Meli, A. A. Lamb, C. Leger, J. Wong, H. Hoffmann, D. Maze, and S. Amarasinghe. "A Stream Compiler for Communication-Exposed Architectures." In Proc. of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002. DOI: 10.1145/605397.605428. 36
129. J. Gummaraju and M. Rosenblum. "Stream Programming on General-Purpose Processors." In Proc. of the 38th Annual ACM/IEEE International Symposium on Microarchitecture, 2005. DOI: 10.1109/MICRO.2005.32. 36
130. H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam, and D. Burger. "Dark Silicon and the End of Multicore Scaling." In Proc. of the 38th Annual International Symposium on Computer Architecture, 2011. DOI: 10.1145/2000064.2000108. 40
131. N. Hardavellas, M. Ferdman, B. Falsaf, and A. Ailamaki. "Toward Dark Silicon in Servers." In IEEE Micro, v. 31, no. 4, 2011. DOI: 10.1109/MM.2011.77.40.