Stealth prefetching

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2006, Pages 274-282

  Cantin, Jason F ^a   Lipasti, Mikko H ^b   Smith, James E ^b  

^a IBM   (United States)

^b Wisconsin Electric Machines and Power Electronics Consortium   (United States)

Author keywords

Coherence; Multiprocessors; Prefetching

Indexed keywords

BASELINE SYSTEMS; MEMORY LATENCY; MULTIPROGRAMMED WORKLOADS; STEALTH PREFETCHING;

DYNAMIC RANDOM ACCESS STORAGE; NATURAL SCIENCES COMPUTING; PROBLEM SOLVING; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

MULTIPROCESSING SYSTEMS;

EID: 34547449252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1168857.1168892     Document Type: Conference Paper

References (22)

1. Charlesworth, A. The Sun Fireplane System Interconnect. In Proceedings of SC2001.
2. Tendler, J., Dodson, S., and Fields, S. IBM eServer Power4 System Microarchitecture, Technical White Paper, IBM Server Group, 2001
3. Kalla, R., Sinharoy, B., and Tendler, J. IBM Power5 Chip: A Dual-Core Multithreaded Processor IEEE Micro, 2004.
4. Weber, F., Opteron and AMD64, A Commodity 64 bit x86 SOC. Presentation. Advanced Micro Devices, 2003.
5. th International Symposium on High-Performance Computer Architecture (HPCA), 2001.
6. Lin, W-F., Burger, D., and Puzak, T., Filtering Superfluous Prefetches using Density Vectors. In Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD), 2001.
7. th Annual International Symposium on Computer Architecture (ISCA), 2003.
8. Wang, Z., McKinley, K., and Burger, D., Combining Software/Hardware Prefetching and Cache Replacement. IBM Austin Center for Advanced Studies Conference (CAS), 2004.
9. th Annual International Symposium on High Performance Computer Architecture, 2004.
10. Hughes, C., and Adve, S., Memory-side Prefetching for Linked Data Structures for Processor-In-Memory Systems. IEEE Journal on Parallel and Distributed Systems, Volume 65, Issue 4, 2005.
11. rd Annual International Symposium on Computer Architecture (ISCA), 2006.
12. Jerger, N., Hill, E., and Lipasti, M., Friendly Fire: Understanding the Effects of Multiprocessor Prefetching. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2006.
13. Moshovos, A., Exploiting Coarse-Grain Non-Shared Regions in Snoopy Coherent Multiprocessors. Computer Engineering Group Technical Report, University of Toronto, December 2003.
14. nd Annual International Symposium on Computer Architecture (ISCA). 2005.
15. nd Annual International Symposium on Computer Architecture (ISCA), 2005.
16. Cantin, J., Moshovos, A., Lipasti, M., Smith, J., and Falsafi, B., "Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays". IEEE Micro Special Issue on Top Picks from 2005 Computer Architecture Conferences, Jan-Feb 2006.
17. th Annual International Symposium on Computer Architecture (ISCA), 1990.
18. th Workshop on Computer Architecture Evaluation Using Commercial Workloads, pp. 13-22, 2002.
19. Keller, T., Maynard, A., Simpson, R., and Bohrer, P., Simos-ppc Full System Simulator. http://www.cs.utexas.edu/users/cart/simOS.
20. UltraSPARC IV Processor, User's Manual Supplement, Sun Microsystems Inc, 2004.
21. Gharachorloo, K., Gupta, A., and Hennessy, J. Two Techniques to Enhance the Performance of Memory Consistency Models. In Proceedings of the International Conference on Parallel Processing (ICPP), 1991.
22. Alameldeen, A., Martin, M., Mauer, C., Moore, K., Xu, M., Hill, M., and Wood, D. Simulating a $2M Commercial Server on a $2K PC. IEEE Computer, 2003.