Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 222-233

  Liu, Haiming ^a   Ferdman, Michael ^b   Huh, Jaehyuk ^c   Burger, Doug ^d  

^a University of Texas at Austin   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d MICROSOFT RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE BLOCKS; CACHE EFFICIENCY; DATA CACHES; GENERAL-PURPOSE MICROPROCESSORS; NEW APPROACHES; NEW CLASS; PREDICTION ACCURACY; PREFETCH; PREFETCHING;

MICROPROCESSOR CHIPS;

CACHE MEMORY;

EID: 66749155879     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771793     Document Type: Conference Paper

References (30)

1. J. Abella, A. González, X. Vera, and M. F. P. O'Boyle. IATAC: a smart predictor to turn-off L2 cache lines. ACM Transactions on Architecture and Code Optimization (TACO), 2(1):55-77, March 2005.
2. D. Burger, J. R. Goodman, and A. Kägi. The declining effectiveness of dynamic caching for general-purpose microprocessors. Technical Report 1261, Computer Sciences Department, University of Wisconsin, Madison, 1995.
3. R. Desikan, D. C. Burger, S. W. Keckler, and T. M. Austin. Sim-alpha: a validated, execution-driven alpha 21264 simulator. Technical Report TR-01-23, Computer Sciences Department, University of Texas at Austin, 2001.
4. M. Ferdman and B. Falsafl. Last-touch correlated data streaming. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, 2007.
5. K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leakage power. In Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002.
6. A. Gonzalez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In Proceedings of the 9th International Conference on Supercomputing, 1995.
7. Z. Hu, S. Kaxiras, and M. Martonosi. Timekeeping in the memory system: Predicting and optimizing memory behavior. In Proceedings of the 29th International Symposium on Computer Architecture, 2002.
8. Z. Hu, M. Martonosi, and S. Kaxiras. TCP: Tag correlating prefetchers. In Proceedings of the 9th International Symposium on High Performance Computer Architecture, 2003.
9. J. Huh. Hardware techniques to reduce communication costs in multiprocessors, 2006. Ph.D. Dissertation, Department of Computer Sciences, University of Texas at Austin.
10. J. Jalminger and P. P. Stenstrom. A novel approach to cache block reuse prediction. In Proceedings of the 2003 International Conference on Parallel Processing, 2003.
11. T. L. Johnson, D. A. Connors, M. C. Merten, and W. W. Hwu. Run-time cache bypassing. IEEE Transactions on Computers, 48(12):1338-1354, 1999.
12. M. Kampe, P. Stenström, and M. Dubois. Self-correcting LRU replacement policies. In Proceedings of the 1st conference on Computing frontiers, 2004.
13. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001.
14. M. Kharbutli and Y. Solihin. Counter-based cache replacement and bypassing algorithms. IEEE Transactions on Computers, 57(4):433-447, 2008.
15. A.-C. Lai and B. Falsafl. Selective, accurate, and timely self-invalidation using last-touch prediction. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 139-148, 2000.
16. A.-C. Lai, C. Fide, and B. Falsafl. Dead-block prediction & dead block correlating prefetchers. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 144-154, 2001.
17. A. R. Lebeck and D. A. Wood. Dynamic self-invalidation: Reducing coherence overhead in shared-memory multiprocessors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 48-59, 1995.
18. J. D. McCalpin. Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, December 1995.
19. A. Mendelson, D. Thiébaut, and D. Pradhan. Modeling live and dead lines in cache memory systems. IEEE Transactions on Computers, 42(1):1-14, 1993.
20. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr, and J. Emer. Adaptive insertion policies for high-performance caching. In Proceedings of the 34th Annual International Symposium on Computer Architecture, 2007.
21. R. Rabbah, I. Bratt, K. Asanovic, and A. Agarwal. Versatility and versabench: A new metric and a benchmark suite for flexible architectures. Technical Report MIT-LCS-TM-646, MIT Techincal Memo, June 2004.
22. J. A. Rivers, E. S. Tarn, G. S. Tyson, E. S. Davidson, and M. Farrens. Utilizing resue information in data cache management. In Proceedings of the 12th International Conference on Supercomputing, 1998.
23. J. Sartor, S. Venkiteswaran, K. S. McKinley, and Z. Wang. Cooperative caching with keep-me and evict-me. In The 9th IEEE Annual Workshop on the Interaction between Compilers and Computer Architectures, 2005.
24. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proceedings of the 2001 International Conference on Parallel Architecture and Compilation Techniques, 2001.
25. S. Somogyi, T. F. Wenisch, N. Hardavellas, J. Kim, A. Aila-maki, and B. Falsafl. Memory coherence activity prediction in commercial workloads. In 3rd Workshop on Memory Performance Issues, 2004.
26. P. Stenström. Chip-multiprocessing and beyond. In Keynote at 12th International Symposium on High-Performance Computer Architecture, 2006.
27. G. Tyson, M. Farrens, J. Matthews, and A. R. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th Annual International Symposium on Microarchi-tecture, 1995.
28. Z. Wang, K. S. McKinley, A. L. Rosenberg, and C. C. Weems. Using the compiler to improve cache replacement decisions. In Proceedings of International Conference on Parallel Architectures and Compilation Techniques, 2002.
29. W. A. Wong and J.-L. Baer. Modified LRU policies for improving second-level cache behavior. In Proceedings of 6th International Symposium on High Performance Computer Architecture, 2000.
30. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture.