Enlarging instruction streams

IEEE Transactions on Computers

Volumn 56, Issue 10, 2007, Pages 1342-1357

  Santana, Oliverio J ^a   Ramirez, Alex ^b   Valero, Mateo ^b  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

Access latency; Branch prediction; Code optimization; Instruction fetch; Superscalar processor design

Indexed keywords

CODE CONVERTERS; COMPUTATIONAL COMPLEXITY; OPTIMIZATION; PROGRAM PROCESSORS;

INSTRUCTION STREAM; PREDICTION OVERRIDING; STREAM FETCH ENGINE; TABLE ACCESS LATENCY;

COMPUTER ARCHITECTURE;

EID: 34548767664     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.70742     Document Type: Article

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